Jitter and Spur Minimization in Fractional-N Digital Frequency Synthesizers : Modeling, Simulation, Analysis, and Design Methodologies.

Format:

Book

Author/Creator:

Wang, Xu.

Series:

Analog Circuits and Signal Processing Series

Language:

English

Physical Description:

1 online resource (319 pages)

Edition:

1st ed.

Place of Publication:

Cham : Springer, 2026.

Summary:

This book presents a rigorous and practically grounded treatment of jitter and spur minimization in fractional-N digital phase locked loops (DPLLs), addressing one of the most critical challenges in modern frequency synthesis.

Contents:

Analog Circuits and Signal Processing

Jitter and Spur Minimization in Fractional-N Digital Frequency Synthesizers

Preface

Acknowledgements

Contents

1. Introduction

2. Modeling Methodology for Digital Phase-Locked Loop (DPLL)

3. Enhanced Linearized Analysis of Mid-Rise Time-to-Digital Converter (TDC)

4. Prediction of System Jitter and Output PN

5. Enhanced Jitter Minimization for Integer-N DPLLs and Its Impact on Output PN

6. Analysis of DTC-Assisted Fractional-N DPLL

7. DTC Enhancement Strategies I: DTC Requantization

8. DTC Enhancement Strategies II: Nonlinear DCD

9. Conclusions.

Notes:

Description based on publisher supplied metadata and other sources.

ISBN:

9783032271860

OCLC:

1610751097