Advances in computers. Volume 118 , Durable phase-change memory architectures / edited by Marjan Asadinia and Hamid Sarbazi-Azad.

Format:

Book

Contributor:

Asadinia, Marjan, editor.

Sarbazi-Azad, Hamid, editor.

Hurson, A. R., editor.

Series:

Advances in computers ; 0065-2458 v. 118 (OCoLC)1461174

Advances in computers, 0065-2458 ; v. 118

Language:

English

Subjects (All):

Computer storage devices.

Memory management (Computer science).

Physical Description:

1 online resource (x, 135 pages) : illustrations.

Edition:

First edition.

Other Title:

Durable phase-change memory architectures.

Place of Publication:

Cambridge, Massachusetts : Academic Press, Elsevier, [2020]

Summary:

The 118th volume is an eclectic volume inspired by recent advances in memory technology in general and more specifically on Phase Change Memory (PCM) technology as potential replacement for Dynamic Random Access Memory (DRAM).

Contents:

Chapter 1: Introduction to non-volatile memory technologies

1. Memory hierarchy and non-volatile memory

2. Emerging NVM technologies

3. PCM technology maturity

4. Contributions

5. Organization of the book

References

Chapter 2: The emerging phase change memory

1. Introduction

2. PCM materials/device physics

3. Memory cell and array design

4. Multi-level-cell phase change memory (MLC PCM)

5. Read techniques

6. Write techniques

7. Reliability

Chapter 3: Phase-change memory architectures

1. Architecting PCM for main memories

1.1. PCM organization

1.2. Fine-grained write filtering

1.3. Hybrid memory: Combining DRAM and PCM

2. Tolerating slow writes in PCM

2.1. Write cancellation for PCM

2.2. Write pausing

2.3. PRES: Pseudo-random encoding scheme to increase the bit flip reduction in the memory

3. Wear-leveling for durability

3.1. Start-Gap wear-leveling

3.2. Randomized Start-Gap

4. Secure wear-leveling algorithms

4.1. Region-based Start-Gap (RBSG)

4.2. PCM-S scheme

4.3. Security refresh scheme

4.4. SLC-enabled wear-leveling for MLC PCM

5. Error resilience in phase change memories

5.1. Fault model assumption

5.2. Dynamically replicated memory (DRM)

5.3. Error correcting pointers (ECP)

5.4. Stuck-at-fault error recovery (SAFER)

5.5. Fine-grained embedded redirection (FREE-p)

5.6. A recursively defined invertible set scheme to tolerate multiple stuck-at faults in resistive memory (RDIS)

5.7. Pay-as-you-go: Low-overhead hard error correction for phase change memories (PAYG)

5.8. Zombie scheme

5.9. Aegis method

5.10. Captopril scheme

5.11. Tolerating hard errors using compression.

5.12. Improving performance and lifetime with relaxed write/read

6. Soft error approaches

Chapter 4: Inter-line level schemes for handling hard errors in PCMs

1. OD3P: On-demand page paired PCM

2. Structure and operation of page paired PCM

2.1. Target page selection algorithm

2.2. Pairing algorithm

2.3. Address translation

2.4. Discussion

3. Fixed pairing algorithm

3.1. Pairing algorithm

3.2. Address translation

4. Partially-selective pairing algorithm

4.1. Address translation

5. Operation of different OD3P mechanisms: Examples

6. Line-level OD3P

7. Simulation environment and scenarios

7.1. Infrastructure

7.2. System configuration

7.3. MLC PCM array model

7.4. Workloads

7.5. Metrics

8. Experimental results

8.1. Analysis under synthetic write traffic

8.2. Analysis under real workloads

8.2.1. Performance analysis

8.2.2. Group size in PS-OD3P

8.2.3. Endurance analysis

8.2.4. TPS size analysis

8.2.5. Performance comparison of OD3P and DRM under different bit failures

8.3. Comparison to line-level schemes

9. Hardware overhead and extension for N-bit MLC PCM

Further reading

Chapter 5: Handling hard errors in PCMs by using intra-line level schemes

1. BLESS: A simple and efficient scheme for prolonging PCM lifetime

2. Improving the bit flips uniformity

3. Tolerating the hard errors

3.1. Problem formulation

4. Write operation in BLESS

5. Read operation in BLESS

6. Meta-data information

7. Evaluation setting

8. Methodology

9. Evaluated architectures

10. Evaluation metrics

11. Evaluation results

12. Comparison to page-level schemes

13. Intra-line level pairing (ILP)

14. ILP structure

15. Experimental results

15.1. Analysis under synthetic write traffic

15.2. Analysis under real workloads

16. Data block partitioning for recovering stuck-at faults in PCMs

17. Tolerating hard errors

17.1. Before occurrence of hard errors

17.2. After occurrence of hard errors

17.3. Examples of the proposed method

18. Write operation

19. Read operation

20. Meta-data information

21. Experimental results

21.1. Lifetime

21.2. Average number of recovered errors per block

21.3. Partitioning size effect

21.4. Overall performance

21.5. Number of required shifts

21.6. IntraV

21.7. Latency overhead

Chapter 6: Addressing issues with MLC phase-change memory

1. Variable resistance spectrum assignment

2. The MLC VR-PCM

2.1. VR-PCM for MLC read improvement

2.2. Binary-directed resistance partitioning

2.3. Discussion

3. Extended VR-PCM

4. Ultimate design: Reconfigurable VR-PCM

5. Hardware implementation issues

5.1. Main memory controller

5.2. Frequent value finder logic

5.3. Reassigning resistance levels to data values

5.4. OS support for value translation

6. Simulation results

6.1. VR-PCM for 2-bit MLCs

6.2. Extended vs reconfigurable VR-PCM for high-density MLCs

7. Process variation and resistance drift.

7.1. Analysis of drift tolerance

About the authors.

Notes:

Includes bibliographical references.

Description based on online resource; title from digital title page (viewed on February 26, 2021)

Description based on publisher supplied metadata and other sources.

ISBN:

0-12-818755-7

0-12-818754-9

OCLC:

1141915083