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Design of Power Management Integrated Circuits.
- Format:
- Book
- Author/Creator:
- Wicht, Bernhard.
- Series:
- IEEE Press Series
- Language:
- English
- Subjects (All):
- Integrated circuits--Design and construction.
- Integrated circuits.
- Electric power--Conservation.
- Electric power.
- Physical Description:
- 1 online resource (478 pages)
- Edition:
- 1st ed.
- Place of Publication:
- Newark : John Wiley & Sons, Incorporated, 2024.
- Summary:
- "This book is a comprehensive reference for power management IC design. The book covers the circuit design of main power management circuits like charge pumps, bridge drivers, linear and switched-mode voltage regulators. Sub-circuits include power switches, gate drivers and their supply, level shifters, the error amplifier, current sensing and control loop design. Circuits for protection and diagnostics as well as system design aspects like pin-out, floor planning, grounding/supply guidelines will also be addressed."-- Provided by publisher.
- Contents:
- Cover
- Title Page
- Copyright
- Contents
- Preface
- Chapter 1 Introduction
- 1.1 What Is a Power Management IC and What Are the Key Requirements?
- 1.2 The Smartphone as a Typical Example
- 1.3 Fundamental Concepts
- 1.3.1 Using a Resistor - The Linear Regulator
- 1.3.2 Using Switches and an Inductor - The Inductive DC-DC Converter
- 1.3.3 Switches and Capacitors - The SC Converter
- 1.3.4 Switches and Capacitors and Inductors - The Hybrid Converter
- 1.4 Power Management Systems
- 1.5 Applications
- 1.5.1 IoT Nodes and Energy Harvesting
- 1.5.2 Portable Devices, Smartphones, and Wearables
- 1.5.3 Universal Serial Bus (USB)
- 1.5.4 Drones
- 1.5.5 Telecommunication Infrastructure
- 1.5.6 E‐Bikes
- 1.5.7 Automotive
- 1.5.8 Data Centers
- 1.6 IC Supply Voltages
- 1.7 Power Delivery
- 1.7.1 Lateral and Vertical Power Delivery
- 1.7.2 Integrated Voltage Regulator (IVR)
- 1.7.3 Dynamic Voltage and Frequency Scaling (DVFS)
- 1.7.4 Near‐Threshold Computing
- 1.8 Technology, Components, and Co‐integration
- 1.8.1 Semiconductor Technology
- 1.8.2 Discrete Power Transistors
- 1.8.3 Passive Components
- 1.8.4 Co‐integration
- 1.9 A Look at the Market
- References
- Chapter 2 The Power Stage
- 2.1 Introduction
- 2.2 On‐Resistance and Dropout
- 2.3 Parasitic Capacitances
- 2.4 The Body Diode
- 2.5 Switching Behavior
- 2.5.1 Resistive Load
- 2.5.2 Inductive Load
- 2.5.3 Reverse Recovery and Switching Node Capacitance
- 2.5.4 Power and Gate Loop Inductance
- 2.5.5 Half‐Bridge with Inductive Load
- 2.5.6 Switching Trajectories
- 2.6 Gate Current and Gate Charge
- 2.7 Losses
- 2.7.1 Conduction Losses
- 2.7.2 Conduction Losses in Case of Current Ripple
- 2.7.3 Dynamic Losses
- 2.7.4 Supply Current Related Losses
- 2.7.5 Total Losses
- 2.7.6 Switch Sizing for Minimum Losses
- 2.7.7 Losses in a Half‐Bridge.
- 2.8 Dead Time Generation
- 2.8.1 Fixed Dead Time
- 2.8.2 Adaptive Dead Time
- 2.8.3 Predictive Dead Time
- 2.9 Soft‐Switching
- 2.9.1 Resonant Operation
- 2.9.2 Dead Time Control
- 2.10 Switch Stacking
- 2.11 Back‐to‐Back Configuration
- Chapter 3 Semiconductor Devices
- 3.1 Discrete Power Transistors
- 3.1.1 The Silicon Power MOSFET
- 3.1.2 The Superjunction MOSFET
- 3.1.3 The Insulated‐Gate Bipolar Transistor (IGBT)
- 3.1.4 The Gallium‐Nitride Transistor
- 3.1.5 The Silicon‐Carbide Transistor
- 3.2 Power Transistors in Integrated Circuits
- 3.2.1 Drain‐Extended Transistors
- 3.2.2 Lateral DMOS Transistors
- 3.2.3 Silicon‐on‐Insulator Technologies (SOI)
- 3.2.4 Monolithic GaN Integration
- 3.3 Parasitic Effects
- 3.3.1 Parasitic Bipolar Junction Transistor
- 3.3.2 Capacitive Coupling
- 3.4 Safe Operating Area (SOA)
- 3.5 Integrated Diodes
- 3.5.1 Diodes with a Parasitic PNP Transistor
- 3.5.2 Diodes with a Parasitic NPN Transistor
- 3.5.3 The DMOS Transistor As a Power Diode
- 3.5.4 Zener Diodes
- Chapter 4 Integrated Passives
- 4.1 Capacitors
- 4.1.1 Metal‐Oxide‐Semiconductor Capacitors
- 4.1.2 Metal‐Oxide‐Metal Capacitors
- 4.1.3 Metal‐Insulator‐Metal Capacitors
- 4.1.4 Trench and Ferroelectric Capacitors
- 4.2 Inductors
- 4.2.1 Ampere's Law and Inductance
- 4.2.2 Bond‐Wire and Package‐Layer Inductors
- 4.2.3 Planar Metal‐Layer Inductors
- 4.2.4 Inductors with Magnetic Core
- Chapter 5 Gate Drivers and Level Shifters
- 5.1 Introduction
- 5.2 Gate Driver Configurations
- 5.3 Driver Circuits
- 5.4 DC Characteristics
- 5.5 Driving Strength
- 5.6 The CMOS Inverter as a Gate Driver
- 5.6.1 Input and Output Capacitance
- 5.6.2 Output Current
- 5.6.3 Rise‐Fall Time
- 5.6.4 Average Propagation Delay
- 5.6.5 Power Dissipation.
- 5.7 Gate Driver with a Single‐Stage Inverter
- 5.7.1 Speed
- 5.7.2 Loss Energy
- 5.8 Cascaded Gate Drivers
- 5.8.1 Optimization for Speed
- 5.8.2 Optimization for Energy Efficiency
- 5.9 External Gate Resistor
- 5.10 dv/dt Triggered Turn‐On
- 5.10.1 Integrated Power Stages
- 5.10.2 Discrete Power Stages
- 5.10.3 Save Start‐Up
- 5.11 Bootstrap Gate Supply
- 5.11.1 General Operation
- 5.11.2 Charge Balance and Bootstrap Capacitor Sizing
- 5.11.3 Practical Aspects of Bootstrapping
- 5.11.4 Active Bootstrapping
- 5.12 Level Shifters
- 5.12.1 Resistor‐Based Level Shifters
- 5.12.2 Cross‐Coupled Level Shifters
- 5.12.3 Capacitive Level Shifters
- 5.12.4 Level‐Down Shifters and Ground Level Shifters
- 5.13 Common‐Mode Transient Immunity
- Chapter 6 Protection and Sensing
- 6.1 Overvoltage Protection
- 6.1.1 High‐Voltage Cascode
- 6.1.2 Active Zener Diode
- 6.2 Overvoltage Protection for Inductive Loads
- 6.3 Temperature Sensing and Thermal Protection
- 6.4 Bandgap Voltage and Current Reference
- 6.4.1 Start‐Up Circuit
- 6.4.2 Reference Current Generation
- 6.4.3 Accuracy
- 6.4.4 Trimming
- 6.5 Short Circuits and Open Load
- 6.6 Current Sensing
- 6.6.1 Introduction
- 6.6.2 Replica Sensing
- 6.6.3 Shunt Current Sensing
- 6.6.4 DCR Sensing
- 6.6.5 Current Limit
- 6.7 Zero‐Crossing Detection
- 6.8 Under‐Voltage Lockout
- 6.9 Power‐on Reset
- Chapter 7 Linear Voltage Regulators
- 7.1 Fundamental Circuit and Control Concept
- 7.2 Dropout Voltage
- 7.3 DC Parameters
- 7.3.1 Power Efficiency
- 7.3.2 Current Efficiency
- 7.3.3 Load Regulation
- 7.3.4 Line Regulation
- 7.4 The Error Amplifier
- 7.5 Frequency Behavior and Stability
- 7.5.1 PMOS Type
- 7.5.2 NMOS Type
- 7.6 Transient Behavior
- 7.6.1 Voltage Under‐ and Over‐Shoot
- 7.6.2 Fast Transient Techniques.
- 7.6.3 Slew Rate Enhancement
- 7.6.4 Loop Bandwidth
- 7.7 Noise in Linear Regulators
- 7.8 Power Supply Rejection
- 7.9 Soft‐Start
- 7.10 Capacitor‐Less LDO
- 7.11 Flipped Voltage Follower LDO
- 7.12 The Shunt Regulator
- 7.13 Digital LDOs
- 7.13.1 The Transistor Array
- 7.13.2 The Analog‐to‐Digital Converter
- 7.13.3 The Digital Controller
- 7.13.4 Transient Response
- 7.13.5 Power Supply Rejection
- 7.13.6 Limit Cycle Oscillations
- 7.13.7 Summary
- Chapter 8 Charge Pumps
- 8.1 Introduction
- 8.1.1 Fundamental Circuit and Operation
- 8.1.2 Charge Pumps Applications
- 8.1.3 General Characteristics
- 8.2 Analysis of the Fundamental Charge Pump
- 8.2.1 Step‐Wise Ramp‐Up
- 8.2.2 Voltage Droop for Nonzero Load
- 8.2.3 Output Voltage Ripple
- 8.3 Influence of Parasitics
- 8.3.1 Parasitic Capacitances
- 8.3.2 Finite On‐Resistance
- 8.4 Charge Pump Implementation
- 8.4.1 Charge Pumps with Diodes
- 8.4.2 Charge Pumps with Transistor Switches
- 8.4.3 The Parasitic Bipolar Junction Transistor
- 8.5 Power Efficiency
- 8.6 Cascading of Pumping Stages
- 8.7 Other Charge Pump Configurations
- 8.8 Current‐Source Charge Pumps
- 8.9 Charge Pumps Suitable as a Floating Gate Supply
- 8.10 Closed‐loop Control
- Chapter 9 Capacitive DC-DC Converters
- 9.1 Introduction
- 9.2 Realizable Ratios
- 9.3 Switched‐Capacitor Topologies
- 9.3.1 Series-Parallel
- 9.3.2 Dickson
- 9.3.3 Ladder
- 9.3.4 Fibonacci
- 9.3.5 Conclusion
- 9.4 Gate Drive Techniques
- 9.5 Charge Flow Analysis
- 9.5.1 Charge Flow Vectors
- 9.5.2 Charge Flow Vectors of Common Topologies
- 9.5.3 Ideal Conversion Ratio
- 9.5.4 Equivalent Output Resistance
- 9.6 Output Voltage Ripple
- 9.7 Topology Selection
- 9.8 Capacitor and Switch Sizing
- 9.8.1 Flying Capacitor Sizing
- 9.8.2 Switch Sizing
- 9.8.3 Output Capacitor Sizing.
- 9.9 Loss Analysis and Efficiency
- 9.9.1 Intrinsic Losses
- 9.9.2 Switch Control Losses
- 9.9.3 Parasitic Capacitor Bottom‐Plate Losses
- 9.9.4 Static Losses
- 9.9.5 Loss Minimization
- 9.9.6 Total Losses
- 9.9.7 Efficiency
- 9.10 Multi‐phase SC Converters
- 9.11 Multi‐ratio SC Converters
- 9.11.1 Multi‐ratio Implementation of Common SC Topologies
- 9.11.2 Folding Dickson
- 9.11.3 SAR SC Converters
- 9.11.4 Recursive SC Converters
- 9.12 Multi‐phase Interleaving
- 9.13 Control Methods
- Chapter 10 Inductive DC-DC Converters
- 10.1 The Fundamental Buck Converter
- 10.1.1 Inductor Current
- 10.1.2 On‐/Off‐Times
- 10.1.3 Volt‐Second Balance
- 10.1.4 Voltage Conversion Ratio
- 10.1.5 Current Ripple
- 10.1.6 Inductor Sizing
- 10.1.7 Output Voltage Ripple
- 10.1.8 Capacitor Sizing
- 10.1.9 Switches
- 10.1.10 Asynchronous Rectification
- 10.2 Losses and Power Conversion Efficiency
- 10.3 Closing the Loop
- 10.4 Hysteretic Control
- 10.5 Voltage‐Mode Control (VMC)
- 10.5.1 Direct Duty Control
- 10.5.2 Voltage Feedforward
- 10.5.3 The Sawtooth Generator
- 10.5.4 The Error Amplifier
- 10.5.5 The Comparator
- 10.5.6 Closed‐loop Transfer Function
- 10.5.7 Control‐to‐Output Transfer Function
- 10.5.8 Line‐to‐Output Transfer Function
- 10.6 Current‐Mode Control (CMC)
- 10.6.1 Transfer Function of the Current Loop
- 10.6.2 Control‐to‐Output Transfer Function
- 10.6.3 The Initial Spike
- 10.6.4 Subharmonic Oscillations
- 10.7 Constant On‐Time Control
- 10.8 Frequency Compensation
- 10.8.1 Compensator Types
- 10.8.2 Type I Compensator
- 10.8.3 Type II Compensator
- 10.8.4 Type III Compensator
- 10.8.5 The K‐Factor Method
- 10.8.6 The K‐Factor for Type II Compensation
- 10.8.7 The K‐Factor for Type III Compensation
- 10.8.8 Capacitance Multiplier
- 10.9 Discontinuous Conduction Mode (DCM).
- 10.9.1 General Constant‐Frequency Behavior.
- Notes:
- Description based on publisher supplied metadata and other sources.
- ISBN:
- 1-119-12307-0
- 1-119-12309-7
- OCLC:
- 1434175813
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