A Fast-Turnaround, Easily Testable ASIC Chip for Serial Bus Control Intel Corporation Chandler, AZ

Format:

Conference/Event

Author/Creator:

Ellis, Don, author.

Conference Name:

SAE Future Transportation Technology Conference and Exposition (1987-08-10 : Seattle, Washington, United States)

Language:

English

Physical Description:

1 online resource

Place of Publication:

Warrendale, PA SAE International 1987

Summary:

This paper describes the standard cell ASIC design methodology for a serial bus controller chip. This is a prototype CMOS chip which was designed in 19 weeks for an automotive application. The chip includes testability circuits which help attain 98% fault coverage

Notes:

Vendor supplied data

Publisher Number:

871547

Access Restriction:

Restricted for use by site license