Architecture and Operation of the HIP7030A2 8-Bit J1850 Microcontroller

Format:

Book

Conference/Event

Author/Creator:

Harmon, Joe, author.

Conference Name:

International Congress & Exposition (1995-02-27 : Detroit, Michigan, United States)

Language:

English

Physical Description:

1 online resource cm

Place of Publication:

Warrendale, PA SAE International 1995

Summary:

A 6805 based microcontroller (HIP7030A2) was developed with integrated J1850[1] hardware. Trade-offs were made between hardware and software in terms of cost, speed, memory requirements, and processor overhead. The microcontroller has been used to construct J1850 compliant, single-byte and three-byte header, variable pulse width (VPW) nodes. Algorithms for symbol processing, cyclical redundancy check (CRC) generation/verification, and message filtering were developed which validate the suitability of the HIP7030A2 for stand-alone and dual-processor nodes.Firmware was developed which transforms the HIP7030A2 into a J1850 message coprocessor for single-byte header, VPW messages. Known as the Programmable Communications Interface (PCI) it serves as a slave device to host processors dramatically simplifying the task of J1850 enabling a module

Notes:

Vendor supplied data

Publisher Number:

950034

Access Restriction:

Restricted for use by site license