New Paradigm in Robust Infrastructure Scalability for Autonomous Applications Wayne State University

Format:

Book

Conference/Event

Author/Creator:

Brown, Brown, author.

Conference Name:

WCX SAE World Congress Experience (2019-04-09 : Detroit, Michigan, United States)

Language:

English

Physical Description:

1 online resource cm

Place of Publication:

Warrendale, PA SAE International 2019

Summary:

Artificial Intelligence (A.I.) and Big Data are increasing become more applicable in the development of technology from machine design and mobility to bio-printing and drug discovery. The ability to quantify large amounts of data these systems generate will be paramount to establishing a robust infrastructure for interdisciplinary autonomous applications. This paper purposes an integrated approach to the environment, pre/post data processing, integration, and system security for robust systems in intelligent transportation systems. The systems integration is based on a FPGA embedded system design and computing (EDGE) platform utilizing image processing CNN algorithms from High Energy Physics (HEP) experiments in data centers with associative memory to ROS- FPGA technology in vehicles for hyper-scale infrastructure scalability. The ability to process data in the future is equivalent to collision particle detection that the Large Hadron Collider (LHC) produces at CERN. The future of robust scalability will depend upon how seamlessly several applications can be integrated into a high-performance package with minimal consumption. The proposed architecture will entirely be dependent on a digital network with special attention paid to costs and power consumption needed for a single server platform. In Sect. II, a background of autonomous vehicles, industry analysis, trucking industry shortage, and the automotive industry's race for driverless are provided. Sect. III, outlines the current levels of autonomous and CERN's ability to quantify large amounts of data. Sect. IV, proposes an integrated infrastructure addressing both hardware and interconnected network scalability. Lastly, Sect. V, provides a logic gate analysis, compilation, and simulation of 18 bit NOR gates for Content Addressable Memory (CAM) associative memory design for XOR CMOS used in the ATLAS detector at CERN

Notes:

Vendor supplied data

Publisher Number:

2019-01-0495

Access Restriction:

Restricted for use by site license