An ESL Methodology for Rapid Creation of Embedded Aerospace Systems using Hardware-Software Co-Design on Virtual Platforms Space Codesign Systems Incorporated

Format:

Conference/Event

Author/Creator:

Moss, Moss, author.

Contributor:

Bois, Guy

Dare, Gary

Guerard, Hubert

Conference Name:

SAE 2012 Aerospace Electronics and Avionics Systems Conference (2012-10-30 : Phoenix, Arizona, United States)

Language:

English

Physical Description:

1 online resource

Place of Publication:

Warrendale, PA SAE International 2012

Summary:

This paper presents an Electronic System-Level (ESL) methodology and framework for the system specification, design space exploration, performance analysis, and hardware/software implementation of aerospace electronic systems subject to Quality of Results (QoR) constraints such as execution time, communication rate, technology, as well as Size, Weight and Power (SWaP). In particular, we show how SWaP constraints could be converted into bounds on the target hardware platform, how several potential architectures could be devised for the system, how each potential architecture and mapping could be evaluated for performance, hardware resource usage and power taking into account the impact of Triple Modular Redundancy (TMR), and how a selected architecture could be exported as a hardware/software Register-Transfer Level (RTL) implementation. This methodology is enabled by (and demonstrated with) the SpaceStudio tool suite, a complete HW/SW co-design platform with the unique ability to transform functions between hardware and software as designers decide on the makeup of their system. The methodology and each of its steps are demonstrated on a video Motion-JPEG (M-JPEG) decoder example. 11 different architectures of the M-JPEG were quickly specified and evaluated this way. These architectures used 0 to 5 MicroBlaze or LEON soft-core processors, used CoreConnect or AMBA bus architectures, ran with either bare-metal embedded software or the uCOS/II Real-Time Operating System (RTOS), and differed in their hardware/software partitioning of application tasks. The M-JPEG decoder was also realized on a commercial equivalent of a Virtex-4 radiation-hardened FPGA and results showed that high-level estimates of performance and hardware resource usage were respectively within 15.5% and 17.6% of the final implementation

Notes:

Vendor supplied data

Publisher Number:

2012-01-2133

Access Restriction:

Restricted for use by site license