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Challenges and Mitigations for Data Remanance in FPGA Based Systems Graf Research Corporation, Blacksburg, VA

SAE Technical Papers (1906-current) Available online

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Format:
Book
Conference/Event
Author/Creator:
Paar, Kevin, author.
Contributor:
Harper, Scott
Conference Name:
2024 NDIA Michigan Chapter Ground Vehicle Systems Engineering and Technology Symposium (2024-08-13 : Novi, Michigan, United States)
Language:
English
Physical Description:
1 online resource cm
Place of Publication:
Warrendale, PA SAE International 2024
Summary:
FPGA based electronic systems have the potential to support zeroization and sanitization of sensitive information without resorting to kinetic destruction. However, careful consideration needs to be given to the data remanence effects of both the FPGA and the attached storage media that form a complete system. SRAM, DRAM, and different forms of flash memory all have distinct data remanence characteristics that must be accounted for in the design of zeroization solutions. In this paper, we survey these characteristics across typical FPGA system media types and present a framework to enable the rapid integration of complete zeroization and sanitization capabilities in FPGA systems
Notes:
Vendor supplied data
Publisher Number:
2024-01-4112
Access Restriction:
Restricted for use by site license

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