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Modern Computer Architecture and Organization : A Systems-Level Guide to Modern Computer Architectures, from Hardware Foundations to AI Datacenters.
- Format:
- Book
- Author/Creator:
- Ledin, Jim.
- Language:
- English
- Subjects (All):
- Computer architecture.
- Computer organization.
- Physical Description:
- 1 online resource (736 pages)
- Edition:
- 1st ed.
- Place of Publication:
- Birmingham : Packt Publishing, Limited, 2026.
- Summary:
- Explore modern computer architecture from transistors and instruction sets to cloud-scale systems, LLM platforms, and secure computing, with major updates and new chapters reflecting today's cloud and AI-driven computing landscape Key Features Understand modern processor and system architectures, spanning digital logic through x86/x64, ARM, and.
- Contents:
- Intro
- Modern Computer Architecture and Organization
- Third Edition
- A systems-level guide to modern computer architectures, from hardware foundations to AI datacenters
- Contributors
- About the author
- About the reviewers
- Table of Contents
- Preface
- Preface to the second edition
- Preface to the first edition
- Who this book is for
- What this book covers
- To get the most out of this book
- Download the example code files
- Conventions used
- Get in touch
- Join us on Discord!
- Free benefits with your book
- How to Unlock
- Share your thoughts
- Part 1
- Fundamentals of Computer Architecture
- 1
- Introducing Computer Architecture
- Technical requirements
- The evolution of automated computing devices
- Charles Babbage's Analytical Engine
- ENIAC
- IBM PC
- The Intel 8088 microprocessor
- The Intel 80286 and 80386 microprocessors
- The iPhone
- Moore's law and future trends
- Computer architecture
- Representing numbers with voltage levels
- Binary and hexadecimal numbers
- The 6502 microprocessor
- 6502 arithmetic instructions
- Summary
- Exercises
- Get this book's PDF version and more
- 2
- Digital Logic
- Electrical circuits
- The transistor
- Logic gates
- Latches
- Flip-flops
- Registers
- Adders
- Propagation delay
- Clocking
- Sequential logic
- Hardware description languages
- VHDL
- 3
- Processor Elements
- A simple processor
- Control unit
- Executing an instruction - a simple example
- Arithmetic logic unit
- The instruction set
- Addressing modes
- Immediate addressing mode
- Absolute addressing mode
- Absolute indexed addressing mode
- Indirect indexed addressing mode
- Instruction categories.
- Memory load and store instructions
- Register-to-register data transfer instructions
- Stack instructions
- Arithmetic instructions
- Logical instructions
- Branching instructions
- Subroutine call and return instructions
- Processor flag instructions
- Interrupt-related instructions
- No operation instruction
- Interrupt processing
- processing
- BRK instruction processing
- Input/output operations
- Programmed I/O
- Interrupt-driven I/O
- Direct memory access
- 4
- Computer System Components
- Memory subsystem
- Introducing the MOSFET
- Constructing DRAM circuits with MOSFETs
- The capacitor
- The DRAM bit cell
- DDR5 SDRAM
- Graphics DDR
- High bandwidth memory
- Prefetching
- I/O subsystem
- Parallel and serial data buses
- PCI Express
- SATA
- M.2
- USB
- Thunderbolt
- Graphics displays
- VGA
- DVI
- HDMI
- DisplayPort
- Network interface
- Ethernet
- Wi-Fi
- Keyboard and mouse
- Keyboard
- Mouse
- Modern computer system specifications
- 5
- Hardware-Software Interface
- Device drivers
- The parallel port
- PCIe device drivers
- Device driver structure
- BIOS
- UEFI
- The boot process
- BIOS boot
- UEFI boot
- Trusted Boot
- Embedded devices
- Operating systems
- Processes and threads
- Scheduling algorithms and process priority
- Multiprocessing
- 6
- Specialized Computing Domains
- Real-time computing
- Real-time operating systems
- Digital signal processing
- ADCs and DACs
- DSP hardware features
- Signal processing algorithms
- Convolution
- Digital filtering
- Fast Fourier transform (FFT)
- Examples of specialized architectures.
- Summary
- Part 2
- Processor Architectures and Instruction Sets
- 7
- Processor and Memory Architectures
- The von Neumann, Harvard, and modified Harvard architectures
- The von Neumann architecture
- The Harvard architecture
- The modified Harvard architecture
- Physical and virtual memory
- Paged virtual memory
- Page status bits
- Memory pools
- Memory management unit
- 8
- Performance-Enhancing Techniques
- Cache memory
- Multilevel processor caches
- Static RAM
- Level 1 cache
- Direct-mapped cache
- Set-associative cache
- Fully associative cache
- Processor cache write policies
- Level 2 and level 3 processor caches
- Instruction pipelining
- Superpipelining
- Pipeline hazards
- Micro-operations and register renaming
- Conditional branches
- Simultaneous multithreading
- SIMD processing
- 9
- Specialized Processor Extensions
- Privileged processor modes
- Interrupt and exception handling
- Protection rings
- Supervisor mode and user mode
- System calls
- Floating-point arithmetic
- The 8087 floating-point coprocessor
- The IEEE 754 floating-point standard
- Power management
- Dynamic voltage frequency scaling
- System security management
- Trusted Platform Module
- Thwarting cyber attackers
- 10
- Graphics Processing Units
- GPU processing
- GPU computations
- GPU applications
- GPUs as data processors
- Big data
- Deep learning
- GPU hierarchical structure
- GA102 graphics processor
- Memory and host processor interfaces
- GPC
- SM
- Warp processor
- CUDA core
- Ray tracing core
- GPU memory architecture.
- Tensor operations
- Tensor processing
- Tensor data types
- Subscribe to Deep Engineering
- 11
- Modern Processor Architectures and Instruction Sets
- x86 architecture and instruction set
- The x86 register set
- x86 addressing modes
- Implied addressing
- Register addressing
- Immediate addressing
- Direct memory addressing
- Register indirect addressing
- Indexed addressing
- Based indexed addressing
- Based indexed addressing with scaling
- x86 instruction categories
- Data movement
- Stack manipulation
- Arithmetic and logic
- Conversions
- Control flow
- String manipulation
- Flag manipulation
- Input/output
- Protected mode
- Miscellaneous instructions
- Other instruction categories
- Common instruction patterns
- x86 instruction formats
- x86 assembly language
- x64 architecture and instruction set
- The x64 register set
- x64 instruction categories and formats
- x64 assembly language
- 32-bit ARM architecture and instruction set
- The ARM register set
- ARM addressing modes
- Immediate
- Register direct
- Register indirect
- Register indirect with offset
- Register indirect with offset, pre-incremented
- Register indirect with offset, post-incremented
- Double register indirect
- Double register indirect with scaling
- ARM instruction categories
- Load/store
- Register movement
- Comparisons
- Address computation
- Supervisor mode
- Breakpoint
- Conditional execution
- 32-bit ARM assembly language
- 64-bit ARM architecture and instruction set
- 64-bit ARM assembly language
- 12
- The RISC-V Architecture and Instruction Set
- The RISC-V architecture.
- The RISC-V base instruction set
- Computational instructions
- Control flow instructions
- Memory access instructions
- System instructions
- Pseudo-instructions
- Privilege levels
- RISC-V extensions
- The M extension
- The A extension
- The C extension
- The F and D extensions
- Other extensions
- RISC-V applications
- 64-bit RISC-V
- Standard RISC-V configurations
- RISC-V assembly language
- Implementing RISC-V in an FPGA
- Part 3
- Computer System Architectures
- 13
- Processor Virtualization
- Introducing processor virtualization
- Types of virtualization
- Operating system virtualization
- Application virtualization
- Network virtualization
- Storage virtualization
- Categories of processor virtualization
- Trap-and-emulate virtualization
- Paravirtualization
- Binary translation
- Hardware emulation
- Virtualization challenges
- Unsafe instructions
- Shadow page tables
- Security
- Virtualizing modern processors
- x86 processor virtualization
- x86 hardware virtualization
- ARM processor virtualization
- RISC-V processor virtualization
- Virtualization tools
- VirtualBox
- KVM
- Xen
- QEMU
- VMware Workstation
- VMware ESXi
- Virtualization and cloud computing
- Electrical power consumption
- 14
- Domain-Specific Computer Architectures
- Architecting computer systems to meet unique requirements
- Smartphone architecture
- iPhone 17 Pro Max
- Personal computer architecture
- Alienware Aurora ACT1250 gaming desktop
- Core Ultra 9 branch prediction
- NVIDIA GeForce RTX 5080 GPU
- ACT1250 subsystems
- Warehouse-scale computing architecture
- WSC hardware
- Rack-based servers
- Hardware fault management
- Electrical power consumption.
- The WSC as a multilevel information cache.
- Notes:
- Previous edition: 2022.
- Description based on publisher supplied metadata and other sources.
- ISBN:
- 1-80602-802-6
- 9781806028023
- OCLC:
- 1584458459
- Publisher Number:
- CIPO000357198
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