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1800-2023 : IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language - Redline / Institute of Electrical and Electronics Engineers (IEEE).
- Format:
- Book
- Author/Creator:
- Institute of Electrical and Electronics Engineers (IEEE), author, issuing body.
- Language:
- English
- Subjects (All):
- Verilog (Computer hardware description language).
- Physical Description:
- 1 online resource (xxxviii, 1275 pages) : illustrations
- Place of Publication:
- New York, New York : Institute of Electrical and Electronics Engineers (IEEE), 2024.
- Summary:
- The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages. Keywords: assertions, design automation, design verification, hardware description language, HDL, HDVL, IEEE 1800, PLI, programming language interface, SystemVerilog, Verilog, VPI.
- Notes:
- Description based on publisher supplied metadata and other sources.
- ISBN:
- 979-88-557-1214-8
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