Through-Silicon Vias for 3D Integration / John H. Lau.

Format:

Book

Author/Creator:

Lau, John H., author.

Series:

McGraw-Hill's AccessEngineering

Language:

English

Subjects (All):

Three-dimensional integrated circuits.

Genre:

Electronic books.

Physical Description:

1 online resource

Edition:

First edition.

Place of Publication:

New York, N.Y. : McGraw-Hill Education, [2013]

Language Note:

In English.

Summary:

This professional book focuses on the latest cost- and space-saving methods of 3D integrated circuits-essential for the development of low-cost, high-performance electronic and optoelectronic products.

Contents:

A. About the Author

B. Foreword

C. Preface

D. Acknowledgments

1. Nanotechnology and 3D Integration for the Semiconductor Industry

Introduction

Nanotechnology

Three-Dimensional Integration

Challenges and Outlook of 3D Si Integration

Potential Applications and Challenges of 3D IC Integration

Recent Advances of 2.5D IC Integration (Interposers)

New Trends in TSV Passive Interposers for 3D IC Integration

Embedded 3D IC Integration

Summary and Recommendations

TSV Patents

References

General Readings

2. Through-Silicon Via Technology

Who Invented TSV and When

High-Volume Products with TSV Technology

Via Forming

Dielectric Isolation Layer (Oxide Liner) Deposition

Barrier (Adhesion) Layer and Seed (Metal) Layer Deposition

TSV Filling by Cu Plating

Chemical-Mechanical Polishing of Cu Plating Residues

TSV Cu Reveal

FEOL and BEOL

TSV Processes

3. Through-Silicon Vias: Mechanical, Thermal, and Electrical Behaviors

Mechanical Behavior of TSVs in System-in-Package

Mechanical Behavior of TSVs in Memory-Chip Stacking

Thermal Behaviors of TSVs

Electrical Modeling of TSVs

Electrical Test of Blind TSVs

4. Thin-Wafer Strength Measurement

Piezoresistive Stress Sensors for Thin-Wafer Strength Measurement

Effects of Wafer Back-Grinding on the Mechanical Behavior of Cu?Low-k Chips

5. Thin-Wafer Handling

Wafer Thinning and Thin-Wafer Handling

Adhesive Is the Key

Thin-Wafer Handling Issues and Potential Solutions

Effect of Dicing Tape on Thin-Wafer Handling of Wafers with Cu/Au Pads

Effect of Dicing Tape on Thin-Wafer Handling of Wafers with Cu-Ni-Au UBMs

Effect of Dicing Tape on Thin-Wafer Handling of Interposer with RDLs and Ordinary Solder Bumps

Materials and Equipments for Thin-Wafer Handling

Adhesive and Process Guidelines for Thin-Wafer Handling

3M Wafer Support System

EVG's Temporary Bonding and Debonding System

Thin-Wafer Handling with Carrierless Technology

6. Microbumping, Assembly, and Reliability

Problem Definition

Electroplating Method for Wafer Bumping of Ordinary Solder Bumps

Assembly of 3D IC Integration SiPs

Electroplating Method for Wafer Bumping of Solder Microbumps

Can We Apply the Same Parameters of the Electroplating Method for Ordinary Solder Bumps to Microbumps?

Lead-Free Fine-Pitch Solder Microbumping

Lead-Free Fine-Pitch C2C Solder Microbump Assembly

Wafer Bumping of Lead-Free Ultrafine-Pitch Solder Microbumps

Conclusions and Recommendations

7. Microbump Electromigration

Solder Microjoints with Larger Solder Volumes and Pitch

Solder Microjoints with Smaller Volumes and Pitches

8. Transient Liquid-Phase Bonding: Chip-to-Chip, Chip-to-Wafer, and Wafer-to-Wafer

How Does Low-Temperature Bonding with Solder Work?

Low-Temperature C2C [(SiO2/Si3N4/Ti/Cu) to (SiO2/Si3N4/Ti/Cu/In/Sn/Au)] Bonding

Low-Temperature C2C [(SiO2/Ti/Cu/Au/Sn/In/ Sn/Au) to (SiO2/Ti/Cu/Sn/In/Sn/Au)] Bonding.

Low-Temperature C2W [(SiO2/Ti/Au/Sn/In/Au) to (SiO2/Ti/Au)] Bonding

Low-Temperature W2W [TiCuTiAu to TiCuTiAuSnInSnInAu] Bonding

9. Thermal Management of Three-Dimensional Integrated Circuit Integration

Effects of TSV Interposer on Thermal Performance of 3D Integration SiPs

Thermal Performance of 3D Memory-Chip Stacking

Effect of Thickness of the TSV Chip on Its Hot-Spot Temperature

Thermal Management System with TSVs and Microchannels for 3D Integration SiPs

10. Three-Dimensional Integrated Circuit Packaging

Cost: TSV Technology versus Wire-Bonding Technology

Wire Bonding of Stack Dies on Cu?Low-k Chips

Bare Chip-to-Chip and Face-to-Face Interconnects

Low-Cost, High-Performance, and High-Density SiPs with Face-to-Face Interconnects

Fan-Out-Embedded WLP-to-Chip (Face-to-Face) Interconnects

A Note on Wire-Bonding Reliability

11. Future Trends of 3D Integration

The Trend of 3D Si Integration

The Trend of 3D IC Integration

References.

Notes:

Includes bibliographical references and index.

Electronic reproduction. New York, N.Y. : McGraw Hill, 2013. Mode of access: World Wide Web. System requirements: Web browser. Access may be restricted to users at subscribing institutions.

Description based on cover image and table of contents, viewed on November 23, 2015.

Other Format:

Print version: Through-Silicon Vias for 3D Integration.

ISBN:

9780071785143 (print-ISBN)

0071785140 (print-ISBN)

OCLC:

931505425

Access Restriction:

Restricted for use by site license.