Digital Circuits & Design.

Format:

Book

Author/Creator:

D.P., Kothari.

Kothari D.P.

Contributor:

J.S, Dhillon.

Series:

Always learning.

Always learning

Language:

English

Subjects (All):

Digital integrated circuits--Design and construction--Textbooks.

Digital integrated circuits.

Integrated circuits--Design and construction--Textbooks.

Integrated circuits.

Physical Description:

1 online resource (1081 pages)

Edition:

1st ed.

Place of Publication:

Noida : Pearson India, 2015.

Summary:

This student friendly, practical and example-driven book gives students a solid foundation in the basics of digital circuits and design. The fundamental concepts of digital electronics such as analog/digital signals and waveforms, digital information and digital integrated circuits are discussed in detail using relevant pedagogy.

Contents:

Cover

Title

Copyright

Brief Contents

Contents

Preface

About the Authors

CHAPTER 1 Introduction

1.1 History of Digital Electronics Systems

1.1.1 Evolution of Electronics

1.1.2 Evolution of Transistors

1.1.3 Evolution of ICs

1.2 Signal and Systems

1.3 Analog Signals and Systems

1.3.1 Direct Signals

1.3.2 Alternating Signal

1.3.3 Sinusoidal Signal

1.3.4 Waveform

1.3.5 Cycle

1.3.6 Time Period

1.3.7 Frequency

1.3.8 Peak Value

1.3.9 Peak-to-Peak Value

1.3.10 Instantaneous Value

1.3.11 Periodic Functions

1.4 Digital System and Signals

1.5 Logic Levels and Pulse Waveforms

1.6 Digital Waveform and Binary Information

1.6.1 Data Transfer

1.7 Advantages of Digital Technology

1.8 Limitations of Digital Technology

1.9 Advances in Digital Technology

1.10 Digital Information Storage

1.11 Digital Computing Systems

1.11.1 Advances in Computing Systems

Summary

Multiple Choice Questions

Questions

CHAPTER 2 NUMBER SYSTEM

2.1 Decimal Number System

2.1.1 Conversion of Base-r Number to Decimal Number

2.1.2 Conversion from Decimal Number to Base-r Number

2.1.3 Base-r Arithmetic

2.1.4 Complement Form

2.1.5 Base-r Subtraction using Complement

2.2 Binary Number System

2.2.1 Binary to Decimal Conversion

2.2.2 Decimal to Binary Conversion

2.3 Binary Arithmetic

2.3.1 Binary Addition

2.3.2 Binary Subtraction

2.4 Signed Numbers

2.4.1 Sign Magnitude Representation

2.4.2 One's Complement (Radix-minus-one Complement)

2.4.3 Two's Complement (True Complement)

2.5 Binary Subtraction using Complement

2.5.1 Subtraction with 1's Complement

2.5.2 Binary Subtraction with 2's Complement

2.6 Binary Multiplication

2.7 Binary Division

2.8 Octal Number System

2.8.1 Octal to Binary Conversion.

2.8.2 Binary to Octal Conversion

2.8.3 Octal Arithmetic

2.9 Hexadecimal Number System

2.9.1 Hexadecimal to Binary Conversion

2.9.2 Binary to Hexadecimal Conversion

2.9.3 Hexadecimal to Octal Conversion

2.9.4 Octal to Hexadecimal Conversion

2.9.5 Hexadecimal Arithmetic

2.10 Binary Codes

2.10.1 Weighted and Non-weighted Code

2.10.2 Sequential Codes

2.11 BCD Code

2.11.1 BCD Addition

2.11.2 BCD Subtraction

2.11.3 BCD Subtraction using 9's Complement

2.11.4 BCD Subtraction using 10's Complement

2.12 Excess-3 Code

2.12.1 Xcess-3 (XS-3) Addition

2.12.2 Excess-3 (XS-3) Subtraction

2.12.3 Excess-3 (XS-3) Subtraction using 9's Complement

2.12.4 Excess-3 (XS-3) Subtraction using 10's Complement

2.13 Gray Code

2.13.1 Binary to Gray Code Conversion

2.13.2 Gray to Binary Code Conversion

2.14 Alphanumeric Code

2.14.1 American Standard Code for Information Interchange (ASCII) Code

2.14.2 Extended Binary-coded Decimal Interchange Code (EBCDIC)

2.14.3 Unicode Characters

2.15 Error Detection Codes

2.15.1 Parity

2.15.2 Block Parity

2.15.3 Five-bit Codes

2.15.4 The Biquinary Code

2.15.5 The Ring Counter Code

2.15.6 Check Sums

2.15.7 Error-correcting Code

2.16 Multi-Precision Numbers

2.16.1 Floating-point Numbers

2.16.2 Binary Floating-point Numbers

2.16.3 IEEE Standard for Floating-point Representation

2.16.4 Arithmetic Operations with Floating-point Numbers

Problems

CHAPTER 3 DIGITAL LOGIC

3.1 Basic Gates

3.1.1 OR Gate

3.1.2 AND Gate

3.1.3 NOT Gate

3.1.4 NAND Gate

3.1.5 NOR Gate

3.1.6 EXCLUSIVE-OR Gate

3.1.7 EXCLUSIVE-NOR Gate

3.2 Positive Logic and Negative Logic

3.3 Inhibit Circuits

3.4 7400-Series Integrated Circuits

3.5 ANSI/IEEE Standard Logic Symbols.

3.6 Pulsed Operation of Logic Gates

CHAPTER 4 COMBINATIONAL LOGIC DESIGN

4.1 Combinational Circuits

4.2 Boolean Laws and Theorems

4.2.1 Law of Intersection

4.2.2 Law of Union

4.2.3 Law of Identity

4.2.4 Law of Null

4.2.5 Law of Tautology or Idempotence

4.2.6 Law of Complement or Negation

4.2.7 Law of Double Negation or Involution

4.2.8 Law of Commutation

4.2.9 Law of Association

4.2.10 Law of Distribution

4.2.11 Law of Absorption

4.2.12 Consensus Theorem

4.2.13 Transposition Theorem

4.2.14 De Morgan's Theorem-I

4.2.15 De Morgan's Theorem-II

4.3 Sum-of-product and Product-of-sum Form

4.4 Karnaugh Map (K-Map)

4.4.1 K-Map Set-Up

4.4.2 Mapping of 0's and 1's in the Karnaugh Map

4.4.3 Adjacency Rule

4.4.4 Grouping of 0's and 1's

4.4.5 Determination of Simplified Boolean Function in SOP and POS Form

4.5 Karnaugh Map with 'Don't Care' Conditions

4.6 Five-Variable Karnaugh Map (K-Map)

4.7 Six-Variable Karnaugh Map (K-Map)

4.8 Quine-McCluskey Minimization Procedure

4.8.1 Reduction Techniques

4.8.2 Petrick's Method

4.9 Map-Entered Variable Method

4.10 Realization of Circuit using NAND/NOR Gates Only

4.10.1 AND/OR Conversion to NAND/NAND Networks

4.10.2 AND/OR Conversion to NOR/NOR Networks

4.11 Hazards

4.11.1 Static Hazards

4.11.2 Static-1 Hazards

4.11.3 Static-0 Hazard

4.11.4 Dynamic Hazard

CHAPTER 5 LOGIC CIRCUIT DESIGN: ARITHMETIC OPERATION

5.1 Combinational Circuits

5.2 Binary Adder

5.2.1 Half-Adder

5.2.2 Full-Adder

5.3 Binary Subtractor

5.3.1 Half-Subtractor

5.3.2 Full-Subtractor

5.4 Binary Parallel Adder

5.5 The Look-Ahead Carry Binary Adders.

5.6 Combinational Circuit For Complements

5.6.1 One's Complement

5.6.2 Two's Complement using Binary Parallel Adder

5.6.3 Multifunction from Binary Parallel Adder

5.7 Binary Subtractor using Parallel Adder

5.7.1 Subtraction with One's Complement

5.7.2 Subtraction with Two's Complement

5.8 Binary Multiplier

5.9 Binary Divider

5.10 BCD Adder

5.11 BCD Subtractor using BCD Adder

5.11.1 Nine's Complement

5.11.2 Subtractor using Nine's Complement

5.11.3 Ten's Complement

5.11.4 Subtractor using Ten's Complement

5.12 Excess-3 (XS-3) Code Adders

5.13 Excess-3 (XS-3) Code Subtractor

5.14 Comparator

5.15 Parity Generator

5.15.1 Even-Parity Generator

5.15.2 Odd-Parity Generator

5.15.3 Even-Parity Bit Receiver

5.15.4 Odd-Parity Bit Receiver

5.16 Code Converter

5.17 Arithmetic Logic Unit

5.17.1 Arithmetic Unit Design

5.17.2 Logic Unit Design

5.17.3 Status Register

CHAPTER 6 LOGIC CIRCUIT DESIGN: DATA PROCESSING

6.1 Introduction

6.2 Decoders

6.2.1 One-to-Two Line Decoder

6.2.2 Two-to-Four Line Decoder

6.2.3 Three-to-Eight Line Decoder

6.2.4 BCD-to-Decimal Decoder

6.2.5 Combinational Circuit using Decoder

6.2.6 Cascading of Decoders

6.3 Encoders

6.3.1 Four-to-Two Line Binary Encoder

6.3.2 Four-to-Two Line Priority Encoder

6.3.3 Octal-to-Binary Encoder

6.3.4 Octal-to-Binary Priority Encoder

6.3.5 Decimal-to-BCD Encoder

6.3.6 Decimal-to-BCD Priority Encoder

6.4 Multiplexers

6.4.1 Two-to-One Multiplexer

6.4.2 Four-to-One Multiplexer

6.4.3 Eight-to-One Multiplexer

6.4.4 Sixteen-to-One Multiplexer

6.4.5 Cascading of Multiplexers

6.4.6 Cascading of Multiplexers using Enable

6.4.7 Combinational Circuit using Multiplexer

6.5 Demultiplexers.

6.5.1 One-to-Two Line Demultiplexer

6.5.2 One-to-Four Line Demultiplexer

6.5.3 One-to-Eight Line Demultiplexer

6.5.4 Cascading of Demultiplexers

6.5.5 Cascading of Demultiplexers using Enable

6.5.6 Combinational Circuit using Demultiplexer

6.6 List of IC's

CHAPTER 7 FLIP-FLOPS

7.1 Introduction

7.2 Basic Bistable Element

7.3 SR Latch

7.3.1 SR Latch using NOR Gates

7.3.2 Gated SR Latch using NOR Gates

7.3.3 SR Latch using NAND Gates

7.3.4 Gated SR Latch using NAND Gates

7.3.5 Characteristic Equation of SR-Latch

7.3.6 State Transition Diagram of SR Latch

7.3.7 Excitation Table of SR-Latch

7.3.8 SR-Flip-Flop with Asynchronous Inputs

7.4 Triggering of Latches

7.4.1 Positive (or high) Level Triggering

7.4.2 Negative (or low) Level Triggering

7.4.3 Positive (or leading or rising) Edge Triggering

7.4.4 Negative (or low) Level Triggering

7.4.5 Generation of Spikes

7.4.6 Generation of Pulse at Rising Edge of Clock Pulse

7.4.7 Generation of Pulse at Falling Edge of Clock Pulse

7.4.8 Latch Versus Flip-Flop

7.5 D-Flip-Flop

7.5.1 Characteristic Equation of D-Flip-Flop

7.5.2 State Transition Diagram of D-Flip-Flop

7.5.3 Excitation Table of D-Flip-Flop

7.6 Flip-Flop Timing

7.7 JK-Flip-Flop

7.7.1 Characteristic Equation of JK-Flip-Flop

7.7.2 State Transition Diagram of JK-Flip-Flop

7.7.3 Excitation Table of JK-Flip-Flop

7.8 T-Flip-Flop

7.8.1 Characteristic Equation of T-Flip-Flop

7.8.2 State Transition Diagram of T-Flip-Flop

7.8.3 Excitation Table of T-Flip-Flop

7.9 Race Around Condition

7.10 Master-Slave Flip-Flop

7.11 Edge-Triggered Flip-Flop

7.12 Conversion of Flip-Flops

7.13 List of Flip-Flop ICs

Problems.

CHAPTER 8 DESIGN OF SEQUENTIAL CIRCUITS.

Notes:

Description based on publisher supplied metadata and other sources.

ISBN:

93-325-5908-2

OCLC:

951076292