Low Overhead Memory Subsystem Design for a Multicore Parallel DSP Processor.

Format:

Book

Author/Creator:

Wang, Jian.

Series:

Linköping Studies in Science and Technology : Dissertations

Language:

English

Subjects (All):

Embedded computer systems.

Signal processing.

Physical Description:

1 online resource (208 pages)

Edition:

1st ed.

Other Title:

Linköping Studies in Science and Technology

Place of Publication:

Linköping : Linköping University Electronic Press, 2014.

Summary:

This dissertation by Jian Wang focuses on the design of a low-overhead memory subsystem for a multicore parallel DSP processor. It addresses the challenges posed by the saturation of physical scaling under Moore's Law and the growing demand for computing power. The work introduces the ePUMA platform, an embedded Parallel DSP Platform with Unique Memory Access, which is designed for communication and multimedia applications. The ePUMA processor employs a master-slave heterogeneous multi-core architecture to enhance computing efficiency and flexibility in DSP applications. Key contributions include the design of a distributed memory architecture tailored for streaming applications, incorporating advanced techniques such as conflict-free access parallel memory and a multi-layer network. The research aims to reduce hardware costs while maintaining high arithmetic computing efficiency, achieving over 70% efficiency in DSP algorithms. The intended audience includes researchers and engineers in electrical engineering, particularly those focused on embedded systems and digital signal processing. Generated by AI.

Contents:

Intro

Abstract

Preface

Acknowledgments

Contents

Abbreviations

Chapter 1 Introduction

Chapter 2 High Performance Streaming Computing

Chapter 3 Parallel Processor Architectures

Chapter 4 Parallel Memory and Conflict Free Data Access

Chapter 5 ePUMA: A Multicore DSP Architecture for Streaming Signal Processing

Chapter 6 Memory Subsystem Design

Chapter 7 Software Development and Toolchain Support

Chapter 8 Application Implementations

Chapter 9 Performance and Area Evaluation

Chapter 10 Conclusions and Future Work

Bibliography

Appendix A Master C Library

Appendix B SIMD Scalar Controller C Library.

Notes:

Description based on publisher supplied metadata and other sources.

Part of the metadata in this record was created by AI, based on the text of the resource.

ISBN:

9789175195568

9175195569

OCLC:

927227440