The FPGA Programming Handbook : An Essential Guide to FPGA Design for Transforming Ideas into Hardware Using SystemVerilog and VHDL / Frank Bruno and Guy Eschemann.

Format:

Book

Author/Creator:

Bruno, Frank, author.

Eschemann, Guy, author.

Series:

Expert insight.

Expert insight

Language:

English

Subjects (All):

Systems engineering.

Systems engineering--Cost effectiveness.

Physical Description:

1 online resource (551 pages)

Edition:

Second edition.

Place of Publication:

Birmingham, UK : Packt Publishing Ltd., [2024]

Biography/History:

Bruno Frank: Frank Bruno is an experienced high-performance design engineer specializing in FPGAs with some ASIC experience. He has experience working for companies like SpaceX, GM Cruise, Belvedere Trading, Allston Trading, and Number Nine. He is currently working as an FPGA engineer for Belvedere Trading. Eschemann Guy: Guy Eschemann was an Electrical Engineer with over twenty years of experience designing FPGA-based embedded systems for automotive, industrial, medical, aerospace, military, and telecom applications. He was working as an FPGA engineer at plc2 Design GmbH.

Summary:

In today's tech-driven world, Field Programmable Gate Arrays (FPGAs) are the foundation of many modern systems. Transforming ideas into reality demands a deep dive into FPGA architecture, tools, and design principles. This FPGA book is your companion to mastering FPGA development with SystemVerilog and VHDL. In this edition, you will master both SystemVerilog and VHDL, gaining supreme versatility in FPGA design. These skills open doors to diverse opportunities and projects in the field. Move beyond theory with real-world projects, starting from LED control and progressing to advanced microcontroller applications, which are highly sought after in today's FPGA job market. You will journey from basic Boolean logic circuits to a resource-optimized calculator, showcasing your hardware design prowess. You will elevate your knowledge by designing a Video Graphics Array (VGA) controller, demonstrating your ability to synthesize complex hardware systems. You can use this handbook as your FPGA development guide, where you will master intricacies, ignite creativity, and emerge with the expertise to craft hardware circuits using SystemVerilog and VHDL. The FPGA Programming Handbook isn't just another technical manual; it's your exhilarating journey to master theory and practice, accelerating your FPGA design skills to soaring new heights.

Contents:

Cover

Copyright

Contributors

Table of Contents

Preface

Chapter 1: Introduction to FPGA Architectures

Technical requirements

What is an ASIC?

Why an ASIC or FPGA?

How does a company create a programmable device using an ASIC process?

Introduction to HDLs

Logical versus bitwise operations

Creating gates using HDL

Assign statement (SystemVerilog/Verilog)

Assign statement equivalent (VHDL)

Single line comments

Multiline comments

if statement

Fundamental logic gates

Logical NOT

Logical AND

Logical OR

XOR

More complex operations

Introducing FPGAs

Exploring the Xilinx Artix-7 and 7 series devices

Combinational logic blocks

Storage

Clocking

I/Os

DSP48E1 - Xilinx DSP core in 7 series devices

ASMBL architecture

Evaluation boards

Nexys A7 100T (or 50T)

Summary

Questions

Answers

Further reading

Chapter 2: FPGA Programming Languages and Tools

Hardware

Information on the Nexys A7

Software

Hardware Description Languages (HDLs)

SystemVerilog versus Verilog

SystemVerilog versus VHDL

Introducing Vitis and Vivado

Vivado installation

Design flow

Design definition/specification

Design entry/constraints

Simulation

Synthesis

Implementation

Running the example

Loading the design

Directory structure

Testbench

VHDL testbench

Running a simulation

Program the board

Challenge

Chapter 3: Combinational Logic

Creating FPGA designs

How to create reusable code - parameters and generics

Understanding the basics of HDL design

Introducing data types

Creating arrays

Querying arrays

Assigning to arrays

Handling multiple-driven nets.

Handling signed and unsigned numbers

Adding bits to a signal by concatenating

Casting signed and unsigned numbers

Creating user-defined types

Accessing signals using values with enumerated types

Packaging up code using functions

Creating combinational logic

Handling assignment operators

Incrementing signals

Making decisions - if-then-else

Introducing the case statement (SystemVerilog)

Using the conditional operator to select data

Introducing the case statement (VHDL)

Using custom data types

Creating structures

Creating unions (SystemVerilog)

Project 2 - Creating combinational logic

Simulating using targeted testing

Simulating using randomized testing

Simulating using constrained randomization

Implementing an LOD using the case statement (SystemVerilog)

Controlling implementation using generate

Designing a reusable LOD using a for loop

Setting SELECTOR = DOWN_FOR

Setting SELECTOR = UP_FOR

Counting the number of ones

Implementing an adder/subtractor

Adder

Subtractor

Implementing a Multiplier

Bringing it all together

Adding a latch

Chapter 4: Counting Button Presses

What is a sequential element?

Clocking your design

Looking at a basic register

Creating a Flip-Flops using SystemVerilog

Creating a flip-flop using VHDL

When to use always @() for FF generation

Using non-blocking assignments

Registers in the Artix 7

How to retain state using clock enables

Resetting the FF

Project 3 - Counting Button Presses

Introducing the seven-segment display

Detecting button presses

Analyzing timing

Looking at asynchronous issues

Using the asynchronous signal directly

Problem with push buttons.

Designing a safe implementation

Switching to decimal representation

Introducing the ILA

What about simulation?

Deep dive into synchronization

Why use multiple clocks?

Two-stage synchronizer

Synchronizing control signals

Passing data

Chapter 5: Let's Build a Calculator

What is a state machine?

Writing a purely sequential state machine

Splitting combination and sequential logic in a state machine

Designing a calculator interface

Designing a Moore state machine

Implementing a Mealy state machine

Practical state machine design

Project 4 - Building a Simple Calculator

Packaging for reuse

Coding the top level

Changing frequencies by using a PLL or MMCM

Investigating the divider

Building a non-restoring divider state machine

Simulating the divider

Sizing the intermediate remainder

Project 5 - Keeping cars in line

Creating the state diagram

Displaying our traffic lights

Pulse width modulation

Implementing delays with a counter

Extra challenge

Chapter 6: FPGA Resources and How to Use Them

What is a digital microphone?

What is PDM?

Project 6 - Listening and learning

Simulating the microphone

Introducing storage

Inferring, instantiating, or using the IP catalog to generate RAM

Basic RAM types

Using xpm_cdc for clock domain crossing

Instantiating memories using xpm_memory

Vivado language templates

Using the IP catalog to create memory

Capturing audio data

Project 7 - Using the temperature sensor

Processing and displaying the data

Smoothing out the data (oversampling)

A deeper dive into FIFOs

Constraints

Generating our FIFO

Summary.

Questions

Chapter 7: Math, Parallelism, and Pipelined Design

Introduction to fixed-point numbers

Project 8 - Using fixed-point arithmetic in our temperature sensor

Using fixed-point arithmetic to clean up the bring-up time

Temperature conversion using fixed-point arithmetic

What about floating-point numbers?

Floating-point addition and subtraction

Floating-point multiplication

Floating-point reciprocal

A more practical floating-point operation library

A quick look at the AXI streaming interface

Project 9 - Updating the temperature sensor project to a pipelined floating-point implementation

Fixed-to-floating-point conversion

Floating-point math operations

Float-to-fixed-point conversion

Simulation environment

Parallel designs

ML and AI and massive parallelism

Parallel design - a quick example

Chapter 8: Introduction to AXI

AXI streaming interfaces

Project 10 - Creating IP for Vivado using AXI streaming interfaces

Seven-segment display streaming interface

Developing the adt7420 IP

Understanding the flt_temp core

Introduction to the IP Integrator

IP Integrator debugging

Packaging the project

AXI4 interfaces (full and AXI-Lite)

Developing IPs - AXI-Lite, full, and streaming

Adding an unpackaged IP to the IP Integrator

Completed designs

Chapter 9: Lots of Data? MIG and DDR2

Note on VHDL

Project 11 - Introducing external memory

Introduction to DDR2

Generating a DDR2 controller using the Xilinx MIG

Setting AXI parameters

Setting memory options

Defining the FPGA options.

Modifying the design for use on the board

Introducing a few other external memory types

QDR SRAM

HyperRAM

SPI RAM

Chapter 10: A Better Way to Display - VGA

Project 12 - Introducing the VGA

Defining registers

Coding a simple AXI-Lite interface

Generating timing for the VGA

The VGA monitor timing generator

Displaying text

Requesting memory

Testing the VGA controller

Examining the constraints

Answer

Chapter 11: Bringing It All Together

Investigating the keyboard interface

Project 13 - Handling the keyboard

Testing the PS/2

Project 14 - Bringing it all together

Displaying PS/2 keycodes on the VGA screen

Displaying the temperature sensor data

Adding a custom character to the text ROM

Displaying audio data

Chapter 12: Using the PMOD Connectors - SPI and UART

UART PMOD

ACL2 PMOD

Understanding Peripheral Modules (PMODs)

PMOD Type 1 and 1A

PMOD Type 2 and 2A

PMOD Type 3 and 3A

PMOD Type 4, 5, and 5A

PMOD Type 6 and 6A

PMOD Type 7 and 7A

Introduction to Universal Asynchronous Receiver-Transmitter (UART)

Bus interface

Waveform

Register interface

RBR - Receive Buffer Register

THR - Transmit Holding Register

IER - Interrupt Enable Register

ISR - Interrupt Status Register

FCR - FIFO Control Register

LCR - Line Control Register

MCR - Modem Control Register

LSR - Line Status Register

MSR - Modem Status Register

SCRATCH - Scratch Pad Register

DLL, DLM - Divisor Register LSB and MSB

UART Implementation

CPU Interface

UART Core

My UART origins.

Testing.

Notes:

Description based on publisher supplied metadata and other sources.

Description based on print version record.

ISBN:

9781805121206

1805121200

OCLC:

1432733547