2023 IEEE International Test Conference (ITC) / IEEE.

Format:

Book

Author/Creator:

Institute of Electrical and Electronics Engineers, author, issuing body.

Language:

English

Subjects (All):

Testing--Congresses.

Testing.

Physical Description:

1 online resource (v, 396 pages)

Other Title:

2023 IEEE International Test Conference

Place of Publication:

IEEE

Piscataway : IEEE, 2023.

Contents:

A New Framework for RTL Test Points Insertion Facilitating a “Shift-Left DFTâ€ Strategy,"H.

A Case Study on IEEE 1838 Compliant Multi-Die 3DIC DFT Implementation,"A.

New Algorithm for Fast and Accurate Linearity Testing of High-Resolution SAR ADCs,"A.

Improving Angle of Arrival Estimation Accuracy for mm-Wave Radars,"F.

OATT: Outlier Oriented Alternative Testing and Post-Manufacture Tuning of Mixed-Signal/RF Circuits and Systems,"S.

Low Distortion Sinusoidal Signal Generator with Harmonics Cancellation Using Two Types of Digital Predistortion,"K.

Maximizing Stress Coverage by Novel DFT Techniques and Relaxed Timing Closure,"A.

Novel Methodology to Optimize TAT and Resource Utilization for ATPG Simulations for Large SoCs,"S.

Global Control Signal Defect Diagnosis in Volume Production Environment,"S.

Method for Diagnosing Channel Damage Using FPGA Transceiver,"S.

Method for Adjusting Termination Resistance Using PMU in DC Test,"S.

Transitioning eMRAM from Pilot Project to Volume Production,"C.

Algorithmic Read Resistance Trim for Improving Yield and Reducing Test Time in MRAM,"D.

Machine-Learning Driven Sensor Data Analytics for Yield Enhancement of Wafer Probing,"N.

Domain-Specific Machine Learning Based Minimum Operating Voltage Prediction Using On-Chip Monitor Data,"Y.

Compaction of Functional Broadside Tests for Path Delay Faults Using Clusters of Propagation Lines,"I.

Robust Pattern Generation for Small Delay Faults Under Process Variations,"H.

Logic Test Vehicles for High Resolution Diagnosis of Systematic FEOL/MEOL Yield Detractors,"Y.

IEA-Plot: Conducting Wafer-Based Data Analytics Through Chat,"M.

Improving Efficiency and Robustness of Gaussian Process Based Outlier Detection via Ensemble Learning,"M.

Recognizing Wafer Map Patterns Using Semi-Supervised Contrastive Learning with Optimized Latent Representation Learning and Data Augmentation,"Z.

Wafer-Scale Electrical Characterization of Silicon Quantum Dots from Room to Low Temperatures,"F.

GPU-Based Concurrent Static Learning,"H.

Biochip-PUF: Physically Unclonable Function for Microfluidic Biochips,"N.

Understanding and Improving GPUs' Reliability Combining Beam Experiments with Fault Simulation,"F.

A Full-Stack Approach for Side-Channel Secure ML Hardware,"A.

Towards Robust Deep Neural Networks Against Design-Time and Run-Time Failures,"Y.

High-Speed, Low-Storage Power and Thermal Predictions for ATPG Test Patterns,"Z.

Scan Cell Segmentation Based on Reinforcement Learning for Power-Safe Testing of Monolithic 3D ICs,"S.

Improving Productivity and Efficiency of SSD Manufacturing Self-Test Process by Learning-Based Proactive Defect Prediction,"Y.

Magnetic Coupling Based Test Development for Contact and Interconnect Defects in STT-MRAMs,"S.

Device-Aware Test for Ion Depletion Defects in RRAMs,"H.

Analysis and Characterization of Defects in FeFETs,"D.

Enhanced ML-Based Approach for Functional Safety Improvement in Automotive AMS Circuits,"A.

Preventing Single-Event Double-Node Upsets by Engineering Change Order in Latch Designs,"S.

Measuring Non-Redundant VIA Test-Coverage for Automotive Designs in Lower Process Nodes,"S.

Diagnosis of Systematic Delay Failures Through Subset Relationship Analysis,"B.

Predicting the Resolution of Scan Diagnosis,"M.

Predictor BIST: An “All-in-Oneâ€ Optical Test Solution for CMOS Image Sensors,"J.

ARC-FSM-G: Automatic Security Rule Checking for Finite State Machine at the Netlist Abstraction,"R.

Laser Fault Injection Vulnerability Assessment and Mitigation with Case Study on PG-TVD Logic Cells,"R.

Simply-Track-and-Refresh: Efficient and Scalable Rowhammer Mitigation,"E.

Low cost production scan chain test for compression based designs,"B.

Enhancing Good-Die-in-Bad-Neighborhood Methodology with Wafer-Level Defect Pattern Information,"C.

Enabling In-Field Parametric Testing for RISC-V Cores,"S.

Estimating the Failures and Silent Errors Rates of CPUs Across ISAs and Microarchitectures,"D.

Utilizing ECC Analytics to Improve Memory Lifecycle Management,"C.

SLM Subsystem for Automotive SoC: Case Study on Path Margin Monitor,".

Notes:

Description based on publisher supplied metadata and other sources.

Includes index.

ISBN:

9798350343250