2011 IEEE 19th Annual International Symposium on Modelling, Analysis, and Simulation of Computer and Telecommunication Systems / Institute of Electrical and Electronics Engineers.

Format:

Book

Author/Creator:

Institute of Electrical and Electronics Engineers, issuing body, author.

Language:

English

Subjects (All):

Computer networks--Mathematical models--Congresses.

Computer networks.

Digital computer simulation--Congresses.

Digital computer simulation.

Physical Description:

1 online resource

Place of Publication:

Piscataway, New Jersey : IEEE, 2011.

Summary:

As the evolution of multi-core multi-threaded processors continues, the complexity demanded to perform an extensive trade-off analysis, increases proportionally. Cycle-accurate or trace-driven simulators are too slow to execute the large amount of experiments required to obtain indicative results. To achieve a thorough analysis of the system, software benchmarks or traces are required. In many cases when an analysis is needed most, during the earlier stages of the processor design, benchmarks or traces are not available. Analytical models overcome these limitations but do not provide the fine grain details needed for a deep analysis of these architectures. In this work we present a new methodology to abstract processor architectures, at a level between cycle-accurate and analytical simulators. To apply our methodology we use queueing modeling techniques. Thus, we introduce Q-MAS, a queueing based tool targeting a real chip (the Ultra SPARC T2 processor) and aimed at facilitating the quantification of trade-offs during the design phase of multi-core multi-threaded processor architectures. The results demonstrate that Q-MAS, the tool that we developed, provides accurate results very close to the actual hardware, with a minimal cost of running what-if scenarios.

Notes:

Description based on publisher supplied metadata and other sources.

ISBN:

0-7695-4430-4