Practical digital design : an introduction to VHDL / Bruce Reidenbach.

Format:

Book

Author/Creator:

Reidenbach, Bruce, 1960- author.

Language:

English

Subjects (All):

VHDL (Computer hardware description language).

Physical Description:

1 online resource. 1 online resource.

Place of Publication:

West Lafayette, Indiana : Purdue University Press, [2022]

Summary:

The VHSIC Hardware Description Language (VHDL) is one of the two most popular languages used to design digital logic circuits. This book provides a comprehensive introduction to the syntax and the most commonly used features of VHDL. It also presents a formal digital design process and the best-case design practices that have been developed over more than twenty-five years of VHDL design experience by the author in military ground and satellite communication systems. Unlike other books on this subject, this real-world professional experience captures not only the what of VHDL, but also the how. Throughout the book, recommended methods for performing digital design are presented along with the common pitfalls and the techniques used to successfully avoid them. Written for students learning VHDL for the first time as well as professional development material for experienced engineers, this book's contents minimize design time while maximizing the probability of first-time design success.

Contents:

Cover

PRACTICAL DIGITAL DESIGN

Title

Copyright

Dedication

TABLE OF CONTENTS

PREFACE

ACKNOWLEDGMENTS

ABOUT THE AUTHOR

CHAPTER 1 INTRODUCTION

Target Audience

A Brief History of Digital Design

The Need for a Hardware Description Language

A Brief Tour of a VHDL Model

CHAPTER 2 SIGNALS, TIME, AND THE SIMULATION CYCLE

Signals

Events

Drivers

Delta Time

The Simulation Cycle

CHAPTER 3 THE VHDL DESIGN ENVIRONMENT

Modeling Styles

Design Flow

Data Types

Type Definition

Vector Data Types

Operators and Precedence

Design Libraries

Predefined Packages

STANDARD Package

STD_LOGIC_1164 Package

NUMERIC_STD Package

TEXTIO Package

Type Conversion

Type Qualification

Attributes

VHDL Language Versions

Coding Style

Vertical Alignment

VHDL Identifier Naming Rules

Comments

CHAPTER 4 DECLARATIONS

Syntax Notation

Object Declaration Syntax

Custom Type Declarations

Integer Types

Floating Point Types

Enumerated Types

Array Types

Record Types

Physical Types

Access Types

Alias Declarations

CHAPTER 5 LIBRARIES AND DESIGN UNITS

Library Units

Entity Declaration

Ports

Generics

Architecture Declaration

Package Declaration

Package Body Declaration

Configuration Declaration

Design Units

Context Clause

Summary

CHAPTER 6 CONCURRENT STATEMENTS

Conditional Signal Assignment Statement

Selected Signal Assignment Statement

Waveform Specification

Delay Models

Generate Statement

Component Instantiation

Concurrent Assertion Statement

Component Declaration

Configuration Specification

Component Instantiation Statement

Direct Entity Instantiation

Block Statement

Process Statement

CHAPTER 7 SEQUENTIAL STATEMENTS

Null Statement

Wait Statement.

If Statement

Case Statement

Loop Statement

Loop Control Statements

Assertion and Report Statements

Signal Assignment

Variable Assignment

CHAPTER 8 THE PROCESS STATEMENT

Process Review

Combinatorial Logic

Level Sensitive Latches

Clocked Logic

Process Examples

Register Files

Shift Registers

Adders

Counters

State Machines

Memory Arrays

Process Construction Guidelines

CHAPTER 9 MODELING CASE STUDIES

Modeling Style

Binary Adder

Behavioral Model

Synthesizable Model

Structural Model

Engine Management System

CHAPTER 10 SUBPROGRAMS

Functions

Return Statements

Examples

Overloading

Pure versus Impure Functions

Procedures

Parameter Passing Details

Signal Parameters

Concurrent Procedure Calls

Procedures as Functions

CHAPTER 11 SIMULATION AND TEST BENCHES

Simulation

Simulation Phases

Test Benches

Test Bench Control

Races

Input Drivers

Output Monitors

Test Bench Example

Test Bench Types

Directed Testing

Constrained Random Testing

Golden Vectors

Combination Test Benches

CHAPTER 12 TEST BENCH DEVELOPMENT

Test Bench Templates

Regression Testing

Test Suites

Code Coverage

CHAPTER 13 TEST BENCH CASE STUDIES

Clocked Full Adder

CHAPTER 14 LOGIC SYNTHESIS

Synthesis Phases

Synthesis Steps

Synthesis

Implementation

Implementation Checks

Device Programming

Quartus Prime Synthesis Steps

CHAPTER 15 ASIC AND FPGA TECHNOLOGY

Digital Logic Technology

CMOS Technology

ASIC Implementation

Gate Arrays

FPGAs

CHAPTER 16 SYNTHESIS CODE EXAMPLES

Concurrent Logic

Data Multiplexers

Shift Registers.

Adders

Addition

Subtraction

Overflow Protection

Addition/Subtraction

Clock Dividers

Loop Unrolling

Tri-State I/O Drivers

A More Complex Example

CHAPTER 17 SPECIALIZED CODE EXAMPLES

FPGA Resources

Multipliers

Multiply/Accumulate

RAM Blocks

Distributed RAM

Block RAM

ROM Blocks

RAM Design Examples

RAM-Based Shift Register

RAM-Based FIFO Buffer

CHAPTER 18 STATE MACHINES

State Machine Basics

State Machine Design

Inputs and Outputs

Design Example

CHAPTER 19 FUNCTIONAL DECOMPOSITION

The Functional Decomposition Process

CHAPTER 20 FILTER DESIGN EXAMPLE

Background

Functional Decomposition

Logic Design

Test Bench Development

Logic Synthesis

Architecture Improvement

CHAPTER 21 DESIGN REUSE

Data Handshaking

APPENDIX A CODING STYLE GUIDELINES

APPENDIX B FUNCTIONAL DESCRIPTION EXAMPLE

SPI Interface

APPENDIX C VHDL RESERVED WORDS

STATEMENT INDEX

SUBJECT INDEX.

Notes:

Description based on print version record.

ISBN:

9781612497679

1612497675

OCLC:

1315643039