Guide to Computer Processor Architecture : A RISC-V Approach, with High-Level Synthesis / by Bernard Goossens.

Format:

Book

Author/Creator:

Goossens, Bernard, Author.

Contributor:

SpringerLink (Online service)

Series:

Computer Science (SpringerNature-11645)

Undergraduate topics in computer science 2197-1781

Undergraduate Topics in Computer Science, 2197-1781

Language:

English

Subjects (All):

Microprocessors.

Computer architecture.

Computers.

Microprogramming.

Operating systems (Computers).

Software engineering.

Processor Architectures.

Computer Hardware.

Control Structures and Microprogramming.

Operating Systems.

Software Engineering.

Local Subjects:

Processor Architectures.

Computer Hardware.

Control Structures and Microprogramming.

Operating Systems.

Software Engineering.

Physical Description:

1 online resource (XXV, 439 pages) : 261 illustrations, 196 illustrations in color.

Edition:

1st ed. 2023.

Contained In:

Springer Nature eBook

Place of Publication:

Cham : Springer International Publishing : Imprint: Springer, 2023.

System Details:

text file PDF

Summary:

This unique, accessible textbook presents a succession of implementations of the open-source RISC-V processor. Implementations are offered in increasing difficulty (non-pipelined, pipelined, deeply pipelined, multi-threaded, multicore). Each implementation is shown as a High-Level Synthesis (HLS) code in C++. This facilitates synthesis and testing on an FPGA-based development board (Such a board can be freely obtained from the Xilinx University Program targeting university professors). The book can be useful for several reasons. First, it is a novel way to introduce computer architecture: The codes given can serve as labs for a processor architecture course. Second, the book content is based on the RISC-V Instruction Set Architecture, which is an open-source machine language promising to become the main machine language to be taught, replacing DLX and MIPS. Third, all the designs are implemented through the HLS tool, which is able to translate a C program into an intellectual property (IP). Lastly, HLS will become the new standard for IP implementations, replacing Verilog/VHDL; already there are job positions tied to HLS, with the argument of rapid IP development. Hence, in addition to offering undergraduates a firm introduction, the textbook/guide can also serve engineers willing to implement processors on FPGA, as well as researchers willing to develop RISC-V based hardware simulators. Bernard Goossens is Professor in the Faculty of Sciences at the Université de Perpignan, France. He is author of the French-language book from Springer, Architecture et microarchitecture des processeurs, 2002.

Contents:

Part I. Single core processors

1. Getting Ready

2. Building a RISC-V Processor

3. Building a Pipelined RISC-V Processor

4. Building a RISC-V Processor with a Multi-cycle Pipeline

5. Building a RISC-V Processor with a Multiple Hart Pipeline

Part II. Multiple core processors

6. Connecting IPs

7. A Multi-core RISC-V Processor

8. A Multi-core RISC-V Processor with Multi-hart Cores.

Other Format:

Printed edition:

ISBN:

978-3-031-18023-1

9783031180231

Access Restriction:

Restricted for use by site license.