Data Orchestration in Deep Learning Accelerators / by Tushar Krishna, Hyoukjun Kwon, Angshuman Parashar, Michael Pellauer, Ananda Samajdar.

Format:

Book

Author/Creator:

Krishna, Tushar., Author.

Kwon, Hyoukjun., Author.

Parashar, Angshuman., Author.

Pellauer, Michael., Author.

Samajdar, Ananda., Author.

Series:

Synthesis Lectures on Computer Architecture, 1935-3243

Language:

English

Subjects (All):

Electronic circuits.

Microprocessors.

Computer architecture.

Electronic Circuits and Systems.

Processor Architectures.

Local Subjects:

Electronic Circuits and Systems.

Processor Architectures.

Physical Description:

1 online resource (XVII, 146 p.)

Edition:

1st ed. 2020.

Place of Publication:

Cham : Springer International Publishing : Imprint: Springer, 2020.

Summary:

This Synthesis Lecture focuses on techniques for efficient data orchestration within DNN accelerators. The End of Moore's Law, coupled with the increasing growth in deep learning and other AI applications has led to the emergence of custom Deep Neural Network (DNN) accelerators for energy-efficient inference on edge devices. Modern DNNs have millions of hyper parameters and involve billions of computations; this necessitates extensive data movement from memory to on-chip processing engines. It is well known that the cost of data movement today surpasses the cost of the actual computation; therefore, DNN accelerators require careful orchestration of data across on-chip compute, network, and memory elements to minimize the number of accesses to external DRAM. The book covers DNN dataflows, data reuse, buffer hierarchies, networks-on-chip, and automated design-space exploration. It concludes with data orchestration challenges with compressed and sparse DNNs and future trends. The target audience is students, engineers, and researchers interested in designing high-performance and low-energy accelerators for DNN inference.

Contents:

Preface

Acknowledgments

Introduction to Data Orchestration

Dataflow and Data Reuse

Buffer Hierarchies

Networks-on-Chip

Putting it Together: Architecting a DNN Accelerator

Modeling Accelerator Design Space

Orchestrating Compressed-Sparse Data

Conclusions

Bibliography

Authors' Biographies.

ISBN:

9783031017674

3031017676