2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) / Institute of Electrical and Electronics Engineers.

Format:

Book

Author/Creator:

Institute of Electrical and Electronics Engineers, author, issuing body.

Language:

English

Subjects (All):

Computer architecture--Congresses.

Computer architecture.

Physical Description:

1 online resource (xii, 167 pages) : illustrations

Other Title:

2017 IEEE/ACM International Symposium on Nanoscale Architectures

Place of Publication:

Piscataway : IEEE, 2017.

Summary:

NANOARCH is the annual cross disciplinary forum for the discussion of novel post CMOS nanocomputing directions and emerging nanoscale CMOS The symposium seeks papers on innovative ideas for solutions to the principal challenge facing integrated electronics in the 21st century how to design, fabricate, and integrate nanosystems to overcome the fundamental limitations of CMOS In particular, such systems could (1) contain unconventional nanodevices with unique capabilities, including directions beyond simple switches, (2) introduce new logic and memory concepts, (3) involve novel circuit styles, (4) introduce new concepts for computing, (5) reconfigure and or mask faults at much higher rates than in CMOS, (6) explore security architectures with nanotechnology, (7) involve new paradigms for manufacturing, and (8) rethink the methodologies and design tools involved.

Contents:

A novel SRAM-STT-MRAM hybrid cache implementation improving cache performance,"O.

Compact modeling of high spin transfer torque efficiency double-barrier magnetic tunnel junction,"G.

SkyNet: Memristor-based 3D IC for artificial neural networks,"S.

Mixing circuit based on neural associative memories and nanoelectronic 1S1R cells,"A.

Spatio-temporal learning with arrays of analog nanosynapses,"C.

Design and operational assessment of an intra-cell hybrid L2 cache,"L.

L3EP: Low latency, low energy program-and-verify for triple-level cell phase change memory,"A.

Transient model with interchangeability for dual-gate ambipolar CNTFET logic design,"X.

A compact 8-bit adder design using in-memory memristive computing: Towards solving the Feynman Grand Prize challenge,"D.

Reconfigurable processing in memory architecture based on spin orbit torque,"L.

Automated synthesis of compact multiplier circuits for in-memory computing using ROBDDs,"A.

Linear regression based multi-state logic decomposition approach for efficient hardware implementation,"W.

Verilog A compact model of a ME-MTJ based XNOR/NOR gate,"N.

Proposal for novel magnetic memory device with spin momentum locking materials,"X.

Frequency modulation of spin torque nano oscillator with voltage controlled magnetic anisotropy effect,"Z.

Memcapacitive reservoir computing,"S.

CASPER Configurable design space exploration of programmable architectures for machine learning using beyond moore devices,"D.

Fine-grained 3D reconfigurable computing fabric with RRAM,"M.

Low cost multi-error correction for 3D polyhedral memories,"M.

Low-power multiplexer designs using three-independent-gate field effect transistors,"E.

A logic-in-memory design with 3-terminal magnetic tunnel junction function evaluators for convolutional neural networks,"S.

High performance and energy-efficient in-memory computing architecture based on SOT-MRAM,"Z.

Polymorphic spintronic logic gates for hardware security primitives " Device design and performance benchmarking,"S.

Fully-connected single-layer STT-MTJ-based spiking neural network under process variability,"E.

Non-temporal logic performance of an atomic switch network,"K.

Approximate vector matrix multiplication implementations for neuromorphic applications using memristive crossbars,"W.

Epsilon-greedy strategy for online dictionary learning with realistic memristor array constraints,"F.

Hybrid neural network using binary RRAM devices,"M.

Naive Bayesian inference of handwritten digits using a memristive associative memory,"M.

Architecture, design and technology guidelines for crosspoint memories,"A.

Ultra high density 3D SRAM cell design in Stacked Horizontal Nanowire (SN3D) fabric,"N.

AOI-based data-centric circuits for near-memory processing,"S.

Power-delivery network in 3D ICs: Monolithic 3D vs. Skybridge 3D CMOS,"J.

Energy efficient computation using injection locked bias-field free spin-hall nano-oscillator array with shared heavy metal,"K.

A self-calibrating sense amplifier for a true random number generator using hybrid FinFET-straintronic MTJ,".

Notes:

Description based on publisher supplied metadata and other sources.

ISBN:

1-5090-6037-5