Behavioral Synthesis for Hardware Security / edited by Srinivas Katkoori, Sheikh Ariful Islam.

Format:

Book

Contributor:

Katkoori, Srinivas, Editor.

Islam, Sheikh Ariful., Editor.

SpringerLink (Online service)

Series:

Computer Science (SpringerNature-11645)

Language:

English

Subjects (All):

Electronic circuits.

Cooperating objects (Computer systems).

Microprocessors.

Computer architecture.

Electronic Circuits and Systems.

Cyber-Physical Systems.

Processor Architectures.

Local Subjects:

Electronic Circuits and Systems.

Cyber-Physical Systems.

Processor Architectures.

Physical Description:

1 online resource (XV, 398 pages) : 154 illustrations, 118 illustrations in color.

Edition:

1st ed. 2022.

Contained In:

Springer Nature eBook

Place of Publication:

Cham : Springer International Publishing : Imprint: Springer, 2022.

System Details:

text file PDF

Summary:

This book presents state-of-the-art research results from leading electronic design automation (EDA) researchers on automated approaches for generating cyber-secure, smart hardware. The authors first provide brief background on high-level synthesis principles and motivate the need for secure design during behavioral synthesis. Then they provide readers with synthesis techniques for six automated security solutions, namely, hardware obfuscation, hardware Trojan detection, IP watermarking, state encoding, side channel attack resistance, and information flow tracking. Provides a single-source reference to behavioral synthesis for hardware security; Describes automatic synthesis techniques for algorithmic obfuscation, using code transformations; Includes behavioral synthesis techniques for intellectual property protection.

Contents:

Introduction

Background

Techniques for algorithm-level obfuscation during high-level synthesis

High-level synthesis of key based obfuscated RTL datapaths

RTL Hardware IP protection Using Key-Based Control and Data Flow Obfuscation

Empirical Word-Level Analysis of Arithmetic Module Architectures for Hardware Trojan Susceptibility

Behavioral synthesis techniques for intellectual property protection

Exploring Low Cost Optimal Watermark for Reusable IP Cores During High Level Synthesis

High-Level Synthesis for Side-Channel Defense

On state encoding against power analysis attacks for finite state controllers

Examining the consequences of high-level synthesis optimizations on power side-channel

Towards a timing attack aware high-level synthesis of integrated circuits

High-Level Synthesis with Timing-Sensitive Information Flow Enforcement

Mitigating information leakage during critical communication using S*FSM

Shielding Heterogeneous MPSoCs From Untrustworthy 3PIPs Through Security-Driven Task Scheduling

Securing industrial control system with high level synthesis

Conclusions and open research problems.

Other Format:

Printed edition:

ISBN:

978-3-030-78841-4

9783030788414

Access Restriction:

Restricted for use by site license.