Rad-hard semiconductor memories / Cristiano Calligaro.

Format:

Book

Author/Creator:

Calligaro, Cristiano, author.

Series:

River Publishers series in electronic materials and devices.

River Publishers Series in Electronic Materials and Devices

Language:

English

Subjects (All):

Semiconductor storage devices.

Semiconductors--Effect of radiation on.

Semiconductors.

Physical Description:

1 online resource (418 pages).

Edition:

1st ed.

Place of Publication:

Gistrup, Denmark : River Publishers, [2018]

Summary:

Rad-hard Semiconductor Memories is intended for researchers and professionals interested in understanding how to design and make a preliminary evaluation of rad-hard semiconductor memories, making leverage on standard CMOS manufacturing processes available from different silicon foundries and using different technology nodes.

Contents:

Cover

Half Title

Series Page

Title Page

Copyright Page

Dedication

Table of Contents

Preface

Acknowledgements

List of Contributors

List of Figures

List of Tables

List of Abbreviations

1: Space Radiation Effects in Electronics

1.1 Space Radiation Environment

1.1.1 The Sun

1.1.2 The Sunspot Cycle

1.1.3 Solar Flares and Coronal Mass Ejections

1.1.4 Trapped Particles - Van Allen Belts

1.1.5 South Atlantic Anomaly

1.1.6 Galactic Cosmic Rays

1.1.7 Space Weather

1.1.8 Atmospheric and Ground-Level Radiation Environments

1.1.9 Cosmic Rays

1.1.10 Radionuclides in the Soil

1.1.11 Thermal Neutrons

1.1.12 Artificial Radiation Sources

1.2 Radiation Effect in Materials and Devices

1.2.1 Energetic Charged Particles and Matter

1.2.2 Stopping Nomenclature

1.2.3 General Theory for Electronic Stopping

1.2.4 Stopping Theories and Semi-Empirical Models

1.2.5 Nuclear Stopping Force

1.2.6 Ion-induced Nuclear Reactions

1.3 Radiation Effects in Semiconductors

1.3.1 Generation of Electron-Hole Pairs

1.3.2 Nuclear Reactions

1.3.3 Linear Energy Transfer vs. Electronic Stopping Force

1.3.4 Spatially Restricted LET

1.3.5 Energy Loss Straggling

1.3.6 Applicability of LET

1.3.7 Prediction Tools for Stopping Force

1.3.8 Cumulative Effect: Total Ionizing Dose and Displacement Damage

1.3.9 Single Event Effects

1.3.10 Soft Errors

1.3.11 Hard Errors

1.4 Effect of Radiation on Memory Devices

1.4.1 Structure of a Memory

1.4.2 Classification and Fault Mechanisms in Memories

1.4.3 Memory Accelerated Tests

1.4.4 Test Methods

1.4.5 Static Mode Testing

1.4.6 Dynamic Mode Testing

1.5 Radiation Hardness Assurance Testing

1.5.1 Beam Requirements

1.5.2 TID Tests

1.5.3 TNID Tests

1.5.4 SEE Tests

1.5.5 Sample Preparation.

1.5.6 TID Tests

1.5.7 SEE Tests

1.5.8 Radiation Facilities

1.5.9 ESA European Component Irradiation Facilities (ECIF)

1.5.10 Other Outstanding European Facilities

1.5.11 Other Outstanding Facilities in the World

1.5.12 Accelerated Test for Memories

1.5.13 Memory Test Setup

1.5.14 Notes on Test Result Analysis

1.6 Conclusion

References

2: RHBD Techniques for Memories

2.1 Effect of HEPs on Semiconductor Devices

2.2 Cumulative Effect: TID

2.3 Single Event Latch-Up: SEL

2.4 Single Event Upset: SEU

2.5 From SET to SEU/SEFI/MBU: When a Disturbance Becomes an Error

2.6 Radiation Hardening By Design (RHBD)

2.7 RHBD at Architectural Level

2.8 RHBD at Circuit Level

2.9 RHBD at Layout Level

Conclusion

3: Rad-Hard SRAMs

3.1 SRAM Foundations: Single Port and Multiple Port

3.2 Synchronous or Asynchronous?

3.3 SRAM Architectures

3.4 Embedded SRAMs

3.5 SRAMs' Building Blocks…Rad-Hard of Course

3.5.1 Input Buffers and ATDs

3.5.2 DEMUXs

3.5.3 Sensing

3.6 ECC Foundations: The Hamming Code

4: One-Time Programmable Memories for Harsh Environments

4.1 Introduction

4.1.1 NVM Technology Overview

4.1.2 OTP Application in Harsh Environments

4.2 OTP Memories for Standard CMOS Technologies

4.2.1 Principle of Operation

4.2.2 CMOS OTP Based on Anti-Fuse

4.2.3 Characteristics and Limits

4.3 Rad-Hard CMOS OTP

4.3.1 Critical Features

4.3.2 State of the Art

4.3.3 RHBD Mitigation: Architectures and Layout

4.4 Conclusion

5: Rad-Hard Flash Memories

5.1 Introduction

5.1.1 Non-Volatile Memories Overview

5.1.2 Flash NVM: Principle of Operation

5.1.3 Flash NVM Standard Architecture Overview: NOR vs. NAND

5.1.3.1 NOR-Flash

5.1.3.2 NAND-Flash

5.1.3.3 Summary.

5.2 Radiation-Hard Flash Architecture Study

5.2.1 Critical Features: Introduction of the Differential Cell Architecture

5.2.2 Program - Erase Circuit Analysis

5.2.3 Read &amp

Verify Circuit Analysis

5.2.4 General Architecture Considerations and Internal Bit Structure

5.2.5 Case Study: FP7 SkyFlash Project on Rad-Hard Non-Volatile Memories

5.3 Side-Circuits

5.3.1 Charge Pump Analysis

5.3.2 Charge Pump

5.3.3 Pad-Ring Requirements

5.4 Conclusion

6: Radiation Hardness of Foundry NVM Technologies

6.1 Introduction

6.2 Physical Phenomena in CMOS Devices Under Irradiation and Their Control

6.3. Radiation Hardness of CMOS Logic Memories

6.3.1 Single-Poly EEPROMs

6.3.2 GOX Anti-Fuses

6.3.3 Radioisotope-Powered Memory

6.3.4 Silicon Nitride-Based Memories

6.4 On the Chip Tools for TID Radiation Effects Control

6.4.1 MOS Structures for Monitoring of Radiation-Induced Charges in Dielectrics

6.4.2 FG Devices for Monitoring the TID

6.4.2.1 Introduction

6.4.2.2 C-Sensor Operation Principle

6.4.2.3 Implementation of C-Sensor Principle in CMOS Platform

6.4.2.4 Detecting Different Types of Ionizing Radiation Using C-Sensor

6.5 Conclusion

7: Rad-Hard Resistive Memories

7.1 ReRAM Cell

7.2 ReRAM Array

7.3 ReRAM Architecture

7.4 ReRAM Periphery

7.5 Forming, Setting and Resetting a Resistive Memory

7.6 Resistive OTPs (ROTPs): The ReRAM Pioneers

8: Technologies for Rad-Hard Resistive Memories

8.1 Non-Volatile Memory Technologies

8.1.1 State-Of-The-Art NVMs - Flash Memory

8.1.2 The Way-Out Over Emerging Technologies

8.1.3 ReRAM Technology

8.2 Reliability Issues of 1T-1R-based HfO2 ReRAM Arrays

8.2.1 Retention Results on Amorphous and Polycrystalline Arrays

8.2.2 Set Evolution

8.2.3 Reset Evolution.

8.2.4 Impact of Temperature on Conduction Mechanisms and Switching Parameters in HfO2-based 1T-1R ReRAM Devices

8.3 CMOS Integration of Resistive Memory Cells

8.4 Conclusions

9: New Generation of NVMs Based on Graphene-Related Nanomaterials

9.1 Introduction

9.2 Graphene-Based Non-Volatile Memories

9.2.1 Graphene and Graphitic Layers

9.2.2 Non-volatile Resistive Memories Based on GO and R-GO Oxide Layers

9.3 Other Approaches to Achieve Non-Volatile Memories Using Graphitic Layers

9.3.1 Graphitic-Based Non-Volatile Memory Using a Transistor Configuration

9.3.2 Non-Volatile Flash-Type Memories Based on Graphene/Multi-layered Graphene

9.4 Conclusions

Index

About the Editors.

Notes:

Includes bibliographical references and index.

Description based on print version record.

ISBN:

9781000796582

1000796582

9781003339182

1003339182

9781000793062

1000793060

9788770220194

8770220190

OCLC:

1262680980

Publisher Number:

9788770220200