Birthing the computer : from relays to vacuum tubes / by Stephen H. Kaisler.

Format:

Book

Author/Creator:

Kaisler, Stephen H., author.

Language:

English

Subjects (All):

Computers--History.

Computers.

Physical Description:

1 online resource (376 pages) : illustrations

Edition:

1st ed.

Place of Publication:

Newcastle upon Tyne, England : Cambridge Scholars Publishing, 2016.

Summary:

Birthing the Computer: From Relays to Vacuum Tubes is the first in a multi-volume series on historical computing machines. This series will span the development of computer systems from the Zuse machines of the early 1930s to about 1995 when microprocessors began to be commoditized. Each volume will focus on a range of technologies, or a class of machines or a particular vendor, and will describe the hardware of the machines and its peripherals, the operating system and system software, and its influence upon programming languages. This volume begins with the Zuse machines which were constructed from relays, but contained the basic elements of a computer system, namely input, computing engine, and output. Early machines from Atanasoff and Berry, Aiken, Stibitz, and IBM are described. The transition from relays to vacuum tubes increased speed and performance significantly, and led to the first true computers in ENIAC, EDSAC, and EDVAC which used paper tape and Williams tubes for I/O and storage. These machines were built by universities. Several early machines were purpose built such as Colossus and BINAC, and created with government support and industrial know-how. By the mid-to-late '50s, computing machines were being built by universities (the SSEM, Whirlwind, and IAS machines), governments (the NBS SEAC and SWAC, and several other machines), and industry (the UNIVAC series and the English Electric DEUCE). Most of these machines were constructed using the von Neumann architecture, and represent an evolution of thinking in how computing machines were to operate along with some innovative ideas in software and programming languages. By the end of the 1950s, the design, development, programming and use of computing machines were in full ferment as many new ideas were proposed, many different machines were designed and some were constructed.

Computing machines became a commercial enterprise. Governments receded from building machines to levying requirements and funding construction, while universities continued to explore new architectures, new operating systems, and new programming languages.

Contents:

Intro

Contents

List of Figures

List of Tables

Part I

Chapter One

1.1 The Z1

1.2 The Z2

1.3 The Z3

1.3.1 Z3 Architecture

1.3.2 Memory

1.3.3 Floating Point Registers

1.3.4 Input and Output

1.3.5 Instruction Execution

1.3.6 Instruction Set

1.3.7 Programming the Z3

1.3.8 Z3 Assessment

1.4 The Z4

1.4.1 ETH and the Z4

1.4.2 The Z5

1.5 Plankalkul

1.6 The Z11

1.7 The Z22

1.8 The Z23

1.9 The Z31

1.10 Assessment of Zuse's Computing Machines

Chapter Two

2.1 ABC System Architecture

2.2 The Atanasoff-Mauchly Conflict

2.3 The ABC Reconstructed

2.4 ABC Assessment

Chapter Three

3.1 Model I: The Complex Numerical Calculator

3.2 Model II: The Relay Interpolator

3.3 Model III: The Ballistic Computer

3.4 Model IV: The Error Detector Mark II

3.5 Model V

3.6 Model VI

3.7 Later BTL Machines

3.8 Assessment of Stibitz's Relay Computers

Chapter Four

4.1 Rebuilding Colossus

4.2 Colossus Architecture

4.3 Colossus and Code Breaking

4.4 Assessment of Colossus

Chapter Five

5.1 ASCC System Architecture

5.1.1 Automatic Sequence Unit

5.1.2 Arithmetic Calculations

5.1.3 Interpolators

5.1.4 Special Registers

5.2 I/O System

5.3 Programming the ASCC

5.4 ASCC Assessment

Chapter Six

6.1 Mark II

6.2 Mark III

6.3 Mark IV

6.4 Mark Machines Assessment

Chapter Seven

7.1 SSEC System Architecture

7.1.1 Electronic Storage Units

7.1.2 Relay Storage

7.1.3 Tape Storage

7.1.4 Dial Storage

7.1.5 Pluggable Storage

7.1.6 Program Tapes

7.2 SSEC Reliability

7.3 SSEC Assessment

Chapter Eight

Further Reading

Exercises for the Reader

Part II

Chapter Nine

9.1 ENIAC System Architecture

9.1.1 Accumulators

9.1.2 Control Units

9.1.3 Master Programmer

9.1.4 Arithmetic Units.

9.1.5 Constant Transmitter

9.1.6 Function Table

9.1.7 Input/Output Units

9.2 Later Modifications

9.3 Applying ENIAC

9.4 The ENIAC Women

9.5 Myths and Stories about ENIAC

9.6 Assessment of ENIAC

Chapter Ten

10.1 The Von Neumann Report

10.2 The Patent Dispute

10.3 The "Real" EDVAC

10.4 EDVAC Architecture

10.4.1 System Architecture

10.4.2 Memory System

10.4.3 I/O System

10.4.4 The EDVAC Console

10.4.5 Debugging Support

10.5 EDVAC Instruction Set

10.6 Physical Challenges

10.7 EDVAC Implementation

10.8 EDVAC Software

10.9 EDVAC Applications

10.9.1 EDVAC Operation

10.10 EDVAC Assessment

Chapter Eleven

11.1 EDSAC System Architecture

11.2 The EDSAC Order Code

11.3 Programming the EDSAC

11.3.1 Subroutine Libraries

11.3.2 The Travails of Paper Tape

11.3.3 An EDSAC Simulator

11.4 EDSAC Firsts

11.5 EDSAC 2

11.6 EDSAC Assessment

Chapter Twelve

12.1 The SSEM Architecture

12.2 Assessment of the SSEM

Chapter Thirteen

13.1 System Architecture

13.2 Instruction Set

13.3 BINAC Assessment

Chapter Fourteen

14.1 Pilot ACE System Architecture

14.2 Programming the Pilot ACE

14.3 Pilot ACE Assessment

14.4 The ACE

Chapter Fifteen

15.1 BRLESC I

15.2 BRLESC II

15.3 BRLESC Assessment

Part III

Chapter Sixteen

16.1 ERA 1101 Architecture

16.1.1 System Architecture

16.1.2 I/O Systems

16.1.3 UNIVAC 1101 Instruction Set

16.1.4 The Atlas II

16.2 UNIVAC 1102

16.3 Dissonance at Remington Rand

16.4 Assessment of the UNIVAC 1101

Chapter Seventeen

17.1 UNIVAC 1103 System Architecture

17.1.1 Control Components

17.1.2 Arithmetic Registers

17.1.3 Master Clock

17.2 Storage

17.3 Arithmetic

17.4 Instruction Format

17.4.1 Transmissive Instructions.

17.4.2 Replace Instructions

17.4.3 Split Instructions

17.4.4 Q-Controlled Instructions

17.4.5 Sequenced Instructions

17.4.6 One-Way Conditional Jump Instructions

17.4.7 Two-Way Conditional Jump Instructions

17.4.8 One-Way Unconditional Jump Instructions

17.4.9 External Equipment Instructions

17.4.10 Stop Instructions

17.5 I/O Systems

17.5.1 I/O Registers

17.5.2 Program Interrupts

17.6 UNIVAC 1103A

17.7 UNIVAC 1104

17.8 Assessment of the Early UNIVAC 11xx Machines

Chapter Eighteen

18.1 SEAC

18.1.1 SEAC System Architecture

18.1.2 Applications

18.2 SWAC

18.2.1 System Architecture

18.2.2 Instruction Set

18.2.3 Software

18.3 DYSEAC

18.4 NBS Computer Assessment

Chapter Nineteen

19.1 Whirlwind System Architecture

19.1.1 Arithmetic Unit

19.1.2 Registers

19.1.3 Magnetic Core Memory

19.1.4 Auxiliary Storage

19.1.5 I/O System

19.2 Whirlwind Instruction Set

19.3 Sample Whirlwind Program

19.4 Whirlwind Assessment

Chapter Twenty

20.1 IAS System Architecture

20.2 IAS Orders

20.3 Assessment of the IAS

Chapter Twenty-One

21.1 MANIAC System Architecture

21.2 MANIAC Instruction Set

21.3 Programming the MANIAC

21.4 MANIAC II

21.4.1 MANIAC II System Architecture

21.4.2 Demand Paging

21.4.3 Peripherals

21.5 Chess Playing

21.6 MANIAC III

21.6.1 MANIAC III System Architecture

21.6.2 MANIAC III Instruction Set

21.7 MANIAC Assessment

Chapter Twenty-Two

22.1 ORDVAC System Architecture

22.1.1 Arithmetic and Control Units

22.1.2 Memory

22.1.3 I/O Devices

22.2 Error Checking the ORDVAC

22.3 ORDVAC Instruction Set

22.4 Assessment of ORDVAC

Chapter Twenty-Three

23.1 UNIVAC I at Lawrence Livermore

23.2 Early UNIVAC Orders

23.3 UNIVAC I at the Census Bureau

23.4 UNIVAC I Architecture.

23.4.1 UNIVAC I Memory

23.4.2 UNIVAC I I/O

23.5 UNIVAC I Instruction Set

23.6 UNIVAC I and Programming

23.7 Remington Rand's Problems

23.8 UNIVAC II

23.9 UNIVAC III

23.10 UNIVAC I-III Assessment

Chapter Twenty-Four

24.1 Basic Architecture

24.2 Hardware Configuration

24.3 The Control

24.4 Instruction Highway

24.5 Main Memory

24.6 The Magnetic Store

24.7 I/O Devices

24.8 Instruction Set

24.9 UTECOM

24.10 EASICODE

24.11 Assessment of the DEUCE

Chapter Twenty-Five

25.1 Pegasus Configuration

25.1.1 Control Unit

25.1.2 The Main Store

25.1.3 The Computing Store

25.1.4 Control Panel

25.1.5 I/O System

25.2 Pegasus Instruction Set

25.3 Pegasus I at the British Science Museum

25.4 Pegasus Assessment

Chapter Twenty-Six

26.1 Ferranti Mark I

26.2 Mark I Architecture

26.3 Mark I Instruction Set

26.3.1 Arithmetic and Logical Orders

26.3.2 B-Line Manipulation Orders

26.3.3 Control Transfer Orders

26.3.4 Peripheral and Miscellaneous Orders

26.4 Programming the Ferranti Mark I

26.5 Assessment of the Mark I

Chapter Twenty-Seven

27.1 System Architecture

27.2 Instruction Set

27.3 Mercury Autocode

27.4 Mercury Installations

27.5 Assessment of the Ferranti Machines

Chapter Twenty-Eight

28.1 The File 0 Machine

28.2 The File 1/ File 2 Machines

28.3 Arithmetic and Control Unit

28.4 I/O Systems

28.4.1 I/O Storage

28.4.2 Buffer Storage

28.4.3 High-Speed Storage

28.4.4 Large Capacity Drum

28.5 File Computer Operations

28.6 File Computer Assessment

Chapter Twenty-Nine

29.1 RAMAC Origins

29.2 IBM 305 System Architecture

29.2.1 Processing Unit and Main Memory

29.2.2 Input Card Reader

29.2.3 Output Printer and Punch

29.2.4 System Console

29.3 Instruction Format

29.3.1 Accumulators.

29.4 Controlling the IBM 305

29.5 IBM 350 Disk File

29.6 IBM 305 Assessment

Glossary

References

Index.

Notes:

Includes bibliographical references and index.

Description based on online resource; title from PDF title page (ebrary, viewed March 20, 2017).

ISBN:

1-4438-9631-4

OCLC:

974947797