Microprocessor architectures and systems : RISC, CISC, and DSP / Steve Heath.

Format:

Book

Author/Creator:

Heath, Steve, author.

Language:

English

Subjects (All):

Microprocessors.

Computer architecture.

Physical Description:

1 online resource (303 p.)

Edition:

1st edition

Place of Publication:

Oxford, England : Newnes, 1991.

Language Note:

English

System Details:

text file

Summary:

Microprocessor Architectures and Systems

Contents:

Front Cover; Microprocessor Architectures and Systems: RISC, CISC and DSP; Copyright Page; Dedication; Table of Contents; Preface; Acknowledgements; Chapter 1. Complex instruction setcomputers; 8-bit microprocessors: the precursors of CISC; 8-bit microprocessor register models; Restrictions; Addressing memory; System integrity; Requirements for a new processor architecture; Software compatibility; Enter the MC68000; Complex instructions, microcode and nanocode; The MC68000 hardware; M68000 asynchronous bus; M6800 synchronous bus; Interrupts; Error recovery and control signals; Bus arbitration

Typical systemThe register set; The USER/SUPERVISOR concept; Exceptions and the vector table; Addressing modes; Instruction set; High-level language support; Start of a revolution; The MC68010 virtual memory processor; MC68010 SUPERVISOR resource; Other improvements; The MC68008; The story continues; Chapter 2. 32-bit CISC processors; Enter HCMOS technology; Architectural challenges; The MC68020 32-bit performance standard; The programmer's model; Bus interfaces; Dynamic bus sizing; On-chip instruction cache; Debugging support; Coprocessor interface

MC68881 and MC68882 floating point coprocessorsThe MC68851 paged memory management unit (PMMU); The MC68030 - the first commercial 50 MHz processor; Chapter 3. The RISC challenge; The 80/20 rule; The initial RISC research; The M88000 family; The MC88100 programming model; The MC88100 instruction set; MC88100 external functions; MC88200 cache MMU; The MBUS protocol; Chapter 4. Digital signal processing; Processor requirements; The DSP56000 family; The programming model; Chapter 5. Memory, memory managementand caches; Achieving processor throughput; Partitioning the system; Shadow RAM

DRAM v. SRAMMemory management; Multitasking and user/supervisor conflicts; Cache size and organization; Cache coherency; Implementing memory systems; Conclusions; Chapter 6. Real-time software, interrupts and exceptions; What is real-time software?; Responding to an interrupt; Interrupting the processor; Servicing the interrupt; Locating associated tasks; Context switches; Improving performance; Interrupting an MC88100; MC88100 interrupt service routines; Interrupting the DSP56000; The M68300 family; Conclusions; Chapter 7. Multiprocessing; SISD - Single instruction, single data

SIMD - Single instruction, multiple dataMIMD - Multiple instruction, multiple data; MISD - Multiple instruction, single data; Constructing a MIMD architecture; Fault-tolerant systems; Single- and multiple-threaded operating systems; Chapter 8. Application ideas; 1 MC68020 and MC68030 design techniques for highreliability applications; 2 Upgrading 8-bit systems; 3 Transparent update techniques for digital filters usingthe DSP56000; 4 Motor and servo control; Chapter 9. Semiconductor technology; Silicon technology; CMOS and bipolar technology; Fabrication technology; Packaging

Processor technology

Notes:

Includes index.

Description based on print version record.

ISBN:

1-4832-7824-7