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Architecture of Computing Systems - ARCS 2019 : 32nd International Conference, Copenhagen, Denmark, May 20-23, 2019, Proceedings / edited by Martin Schoeberl, Christian Hochberger, Sascha Uhrig, Jürgen Brehm, Thilo Pionteck.
SpringerLink Books Lecture Notes In Computer Science (LNCS) (1997-2024) Available online
View online- Format:
- Book
- Series:
- Computer Science (Springer-11645)
- LNCS sublibrary. Theoretical computer science and general issues ; SL 1, 11479.
- Theoretical Computer Science and General Issues ; 11479
- Language:
- English
- Subjects (All):
- Computer networks.
- Operating systems (Computers).
- Logic design.
- Computer architecture.
- Computer input-output equipment.
- Microprocessors.
- Computer Communication Networks.
- Operating Systems.
- Logic Design.
- Computer System Implementation.
- Input/Output and Data Communications.
- Processor Architectures.
- Local Subjects:
- Computer Communication Networks.
- Operating Systems.
- Logic Design.
- Computer System Implementation.
- Input/Output and Data Communications.
- Processor Architectures.
- Physical Description:
- 1 online resource (XIX, 335 pages) : 212 illustrations, 88 illustrations in color.
- Edition:
- First edition 2019.
- Contained In:
- Springer eBooks
- Place of Publication:
- Cham : Springer International Publishing : Imprint: Springer, 2019.
- System Details:
- text file PDF
- Summary:
- This book constitutes the proceedings of the 32nd International Conference on Architecture of Computing Systems, ARCS 2019, held in Copenhagen, Denmark, in May 2019. The 24 full papers presented in this volume were carefully reviewed and selected from 40 submissions. ARCS has always been a conference attracting leading-edge research outcomes in Computer Architecture and Operating Systems, including a wide spectrum of topics ranging from embedded and real-time systems all the way to large-scale and parallel systems. The selected papers are organized in the following topical sections: Dependable systems; real-time systems; special applications; architecture; memory hierarchy; FPGA; energy awareness; NoC/SoC. The chapter 'MEMPower: Data-Aware GPU Memory Power Model' is open access under a CC BY 4.0 license at link.springer.com.
- Contents:
- Dependable Systems
- Hardware/Software Co-designed Security Extensions for Embedded Devices
- SDES - Scalable Software Support for Dependable Embedded Systems
- Real-Time Systems
- Asynchronous Critical Sections in Real-Time Multiprocessor Systems
- Resource-Aware Parameter Tuning for Real-Time Applications
- A Hybrid NoC Enabling Fail-Operational and Hard Real-Time Communication in MPSoC
- Special Applications
- DSL-based Acceleration of Automotive Environment Perception and Mapping Algorithms for embedded CPUs, GPUs, and FPGAs
- Applying the Concept of Artificial DNA and Hormone System to a Low-Performance Automotive Environment
- A Parallel Adaptive Swarm Search Framework for Solving Black-Box Optimization Problems
- Architecture
- Leros: the Return of the Accumulator Machine
- A Generic Functional Simulation of Heterogeneous Systems
- Evaluating Dynamic Task Scheduling in a Task-based Runtime System for Heterogeneous Architectures
- Dynamic Scheduling of Pipelined Functional Units in Coarse-Grained Reconfigurable Array Elements
- Memory Hierarchy
- CyPhOS { A Component-based Cache-Aware Multi-Core Operating System
- Investigation of L2-Cache interferences in a NXP QorIQ T4240 multicore processor
- MEMPower: Data-Aware GPU Memory Power Model
- FPGA
- Effective FPGA Architecture for General CRC
- Receive-Side Notification for Enhanced RDMA in FPGA Based Networks
- An Efficient FPGA Accelerator Design for Optimized CNNs using OpenCL
- Energy Awareness
- The Return of Power Gating: Smart Leakage Energy Reductions in Modern Out-of-Order Processor Architectures
- A Heterogeneous and Reconfigurable Embedded Architecture for Energy-efficient Execution of Convolutional Neural Networks
- An energy efficient embedded processor for hard real-time Java applications
- NoC/SoC
- A Minimal Network Interface for a Simple Network-on-Chip
- Network Coding in Networks-on-Chip with Lossy Links
- Application Specific Reconfigurable SoC Interconnection Network Architectures.
- Other Format:
- Printed edition:
- ISBN:
- 978-3-030-18656-2
- 9783030186562
- Access Restriction:
- Restricted for use by site license.
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