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Formal Methods in Computer-Aided Design : Second International Conference, FMCAD '98, Palo Alto, CA, USA, November 4-6, 1998, Proceedings / edited by Ganesh Gopalakrishnan, Phillip Windley.
LIBRA Q341 .P7 2004
Available from offsite location
- Format:
- Book
- Series:
- Computer Science (Springer-11645)
- Lecture notes in computer science 0302-9743 ; 1522.
- Lecture Notes in Computer Science, 0302-9743 ; 1522
- Language:
- English
- Subjects (All):
- Computer-aided engineering.
- Computer hardware.
- Computer logic.
- Logic, Symbolic and mathematical.
- Computational complexity.
- Computer-Aided Engineering (CAD, CAE) and Design.
- Computer Hardware.
- Logics and Meanings of Programs.
- Mathematical Logic and Formal Languages.
- Complexity.
- Local Subjects:
- Computer-Aided Engineering (CAD, CAE) and Design.
- Computer Hardware.
- Logics and Meanings of Programs.
- Mathematical Logic and Formal Languages.
- Complexity.
- Physical Description:
- 1 online resource (X, 538 pages).
- Edition:
- First edition 1998.
- Contained In:
- Springer eBooks
- Place of Publication:
- Berlin, Heidelberg : Springer Berlin Heidelberg : Imprint: Springer, 1998.
- System Details:
- text file PDF
- Contents:
- Minimalist Proof Assistants: Interactions of Technology and Methodology in Formal System Level Verification
- Reducing Manual Abstraction in Formal Verification of Out- of- Order Execution
- Bit-Level Abstraction in the Verification of Pipelined Microprocessors by Correspondence Checking
- Solving Bit-Vector Equations
- The Formal Design of 1M-Gate ASICs
- Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations
- A Tutorial on Stålmarck's Proof Procedure for Propositional Logic
- Almana: A BDD Minimization Tool Integrating Heuristic and RewritingMethods
- Bisimulation Minimization in an Automata-Theoretic Verification Framework
- Automatic Verification of Mixed-Level Logic Circuits
- A Timed Automaton-Based Method for Accurate Computation of Circuit Delay in the Presence of Cross-Talk
- Maximum Time Separation of Events in Cyclic Systems with Linear and Latest Timing Constraints
- Using MTBDDs for Composition and Model Checking of Real-Time Systems
- Formal Methods in CAD from an Industrial Perspective
- A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool
- Combined Formal Post- and Presynthesis Verification in High Level Synthesis
- Formalization and Proof of a Solution to the PCI 2.1 Bus Transaction Ordering Problem
- A Performance Study of BDD-Based Model Checking
- Symbolic Model Checking Visualization
- Input Elimination and Abstraction in Model Checking
- Symbolic Simulation of the JEM1 Microprocessor
- Symbolic Simulation: An ACL2 Approach
- Verification of Data-Insensitive Circuits: An In-Order-Retirement Case Study
- Combining Symbolic Model Checking with Uninterpreted Functions for Out-of-Order Processor Verification
- Formally Verifying Data and Control with Weak Reachability Invariants
- Generalized Reversible Rules
- An Assume-Guarantee Rule for Checking Simulation
- Three Approaches to Hardware Verification: HOL, MDG, and VIS Compared
- An Instruction Set Process Calculus
- Techniques for Implicit State Enumeration of EFSMs
- Model Checking on Product Structures
- BDDNOW: A Parallel BDD Package
- Model Checking VHDL with CV
- Alexandria: A Tool for Hierarchical Verification
- PV: An Explicit Enumeration Model-Checker.
- Other Format:
- Printed edition:
- ISBN:
- 978-3-540-49519-2
- 9783540495192
- Access Restriction:
- Restricted for use by site license.
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