Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation : 12th International Workshop, PATMOS 2002, Seville, Spain, September 11 - 13, 2002 / edited by Bertrand Hochet, Antonio J. Acosta, Manuel J. Bellido.

Format:

Book

Contributor:

Hochet, Bertrand, 1961- editor.

Acosta, Antonio J., 1966- editor.

Bellido, Manuel J., 1964- editor.

SpringerLink (Online service)

Series:

Computer Science (Springer-11645)

Lecture notes in computer science 0302-9743 ; 2451.

Lecture Notes in Computer Science, 0302-9743 ; 2451

Language:

English

Subjects (All):

Electronic circuits.

Applied mathematics.

Engineering mathematics.

Computer science--Mathematics.

Computer science.

Computer hardware.

Microprocessors.

Computer system failures.

Circuits and Systems.

Mathematical and Computational Engineering.

Mathematics of Computing.

Computer Hardware.

Processor Architectures.

System Performance and Evaluation.

Local Subjects:

Circuits and Systems.

Mathematical and Computational Engineering.

Mathematics of Computing.

Computer Hardware.

Processor Architectures.

System Performance and Evaluation.

Physical Description:

1 online resource (XVI, 500 pages).

Edition:

First edition 2002.

Contained In:

Springer eBooks

Place of Publication:

Berlin, Heidelberg : Springer Berlin Heidelberg : Imprint: Springer, 2002.

System Details:

text file PDF

Summary:

The International Workshop on Power and Timing Modeling, Optimization, and Simulation PATMOS 2002, was the 12th in a series of international workshops 1 previously held in several places in Europe. PATMOS has over the years evolved into a well-established and outstanding series of open European events on power and timing aspects of integrated circuit design. The increased interest, espe- ally in low-power design, has added further momentum to the interest in this workshop. Despite its growth, the workshop can still be considered as a very - cused conference, featuring high-level scienti?c presentations together with open discussions in a free and easy environment. This year, the workshop has been opened to both regular papers and poster presentations. The increasing number of worldwide high-quality submissions is a measure of the global interest of the international scienti?c community in the topics covered by PATMOS. The objective of this workshop is to provide a forum to discuss and inves- gate the emerging problems in the design methodologies and CAD-tools for the new generation of IC technologies. A major emphasis of the technical program is on speed and low-power aspects with particular regard to modeling, char- terization, design, and architectures. The technical program of PATMOS 2002 included nine sessions dedicated to most important and current topics on power and timing modeling, optimization, and simulation. The three invited talks try to give a global overview of the issues in low-power and/or high-performance circuit design.

Contents:

Opening

The First Quartz Electronic Watch

Arithmetics

An Improved Power Macro-Model for Arithmetic Datapath Components

Performance Comparison of VLSI Adders Using Logical Effort

MDSP: A High-Performance Low-Power DSP Architecture

Low-Level Modeling and Characterization

Impact of Technology in Power-Grid-Induced Noise

Exploiting Metal Layer Characteristics for Low-Power Routing

Crosstalk Measurement Technique for CMOS ICs

Instrumentation Set-up for Instruction Level Power Modeling

Asynchronous and Adiabatic Techniques

Low-Power Asynchronous A/D Conversion

Optimal Two-Level Delay - Insensitive Implementation of Logic Functions

Resonant Multistage Charging of Dominant Capacitances

A New Methodology to Design Low-Power Asynchronous Circuits

Designing Carry Look-Ahead Adders with an Adiabatic Logic Standard-Cell Library

CAD Tools and Algorithms

Clocking and Clocked Storage Elements in Multi-GHz Environment

Dual Supply Voltage Scaling in a Conventional Power-Driven Logic Synthesis Environment

Transistor Level Synthesis Dedicated to Fast I.P. Prototyping

Robust SAT-Based Search Algorithm for Leakage Power Reduction

Timing

PA-ZSA (Power-Aware Zero-Slack Algorithm): A Graph-Based Timing Analysis for Ultra-Low Power CMOS VLSI

A New Methodology for Efficient Synchronization of RNS-Based VLSI Systems

Clock Distribution Network Optimization under Self-Heating and Timing Constraints

A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches

Gate-Level Modeling

A Compact Charge-Based Propagation Delay Model for Submicronic CMOS Buffers

Output Waveform Evaluation of Basic Pass Transistor Structure

An Approach to Energy Consumption Modeling in RC Ladder Circuits

Structure Independent Representation of Output Transition Time for CMOS Library

Memory Optimization

A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors

Design and Realization of a Low Power Register File Using Energy Model

Register File Energy Reduction by Operand Data Reuse

Energy-Efficient Design of the Reorder Buffer

High-Level Modeling and Design

Trends in Ultralow-Voltage RAM Technology

Offine Data Profiling Techniques to Enhance Memory Compression in Embedded Systems

Performance and Power Comparative Study of Discrete Wavelet Transform on Programmable Processors

Power Consumption Estimation of a C Program for Data-Intensive Applications

Communications Modeling and Activity Reduction

A Low Overhead Auto-Optimizing Bus Encoding Scheme for Low Power Data Transmission

Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level

Low-Power FSMs in FPGA: Encoding Alternatives

Synthetic Generation of Events for Address-Event-Representation Communications

Posters

Reducing Energy Consumption via Low-Cost Value Prediction

Dynamic Voltage Scheduling for Real Time Asynchronous Systems

Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level

Power Efficient Vector Quantization Design Using Pixel Truncation

Minimizing Spurious Switching Activities in CMOS Circuits

Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic Gates

Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines

Selective Clock-Gating for Low Power/Low Noise Synchronous Counters

Probabilistic Power Estimation for Digital Signal Processing Architectures

Modeling of Propagation Delay of a First Order Circuit with a Ramp Input

Characterization of Normal Propagation Delay for Delay Degradation Model (DDM)

Automated Design Methodology for CMOS Analog Circuit Blocks in Complex Systems.

Other Format:

Printed edition:

ISBN:

978-3-540-45716-9

9783540457169

Access Restriction:

Restricted for use by site license.