High Performance Embedded Architectures and Compilers : First International Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings / edited by Tom Conte, Nacho Navarro, Wen-mei W. Hwu, Mateo Valero, Theo Ungerer.

Format:

Book

Contributor:

Conte, Tom, editor.

Navarro, Nacho, editor.

Hwu, Wen-mei W., editor.

Valero, Mateo, editor.

Ungerer, Theo, 1954- editor.

SpringerLink (Online service)

Series:

Computer Science (Springer-11645)

LNCS sublibrary. Theoretical computer science and general issues ; SL 1, 3793.

Theoretical Computer Science and General Issues ; 3793

Language:

English

Subjects (All):

Computer arithmetic and logic units.

Computer architecture.

Programming languages (Electronic computers).

Computer input-output equipment.

Logic design.

Microprocessors.

Arithmetic and Logic Structures.

Computer System Implementation.

Programming Languages, Compilers, Interpreters.

Input/Output and Data Communications.

Logic Design.

Processor Architectures.

Local Subjects:

Arithmetic and Logic Structures.

Computer System Implementation.

Programming Languages, Compilers, Interpreters.

Input/Output and Data Communications.

Logic Design.

Processor Architectures.

Physical Description:

1 online resource (XIV, 318 pages).

Edition:

First edition 2005.

Contained In:

Springer eBooks

Place of Publication:

Berlin, Heidelberg : Springer Berlin Heidelberg : Imprint: Springer, 2005.

System Details:

text file PDF

Summary:

As Chairmen of HiPEAC 2005, we have the pleasure of welcoming you to the proceedings of the ?rst international conference promoted by the HiPEAC N- work of Excellence. During the last year, HiPEAC has been building its clusters of researchers in computer architecture and advanced compiler techniques for embedded and high-performance computers. Recently, the Summer School has been the seed for a fruitful collaboration of renowned international faculty and young researchers from 23 countries with fresh new ideas. Now, the conference promises to be among the premier forums for discussion and debate on these research topics. Theprestigeofasymposiumismainlydeterminedbythequalityofitstech- cal program. This ?rst programlived up to our high expectations, thanks to the largenumber of strong submissions. The ProgramCommittee received a total of 84 submissions; only 17 were selected for presentation as full-length papers and another one as an invited paper. Each paper was rigorously reviewed by three ProgramCommittee members and at least one external referee. Many reviewers spent a great amount of e?ort to provide detailed feedback. In many cases, such feedback along with constructive shepherding resulted in dramatic improvement in the quality of accepted papers. The names of the Program Committee m- bers and the referees are listed in the proceedings. The net result of this team e?ort is that the symposium proceedings include outstanding contributions by authors from nine countries in three continents. In addition to paper presentations, this ?rst HiPEAC conference featured two keynotes delivered by prominent researchers from industry and academia.

Contents:

Invited Program

Keynote 1: Using EEMBC Benchmarks to Understand Processor Behavior in Embedded Applications

Keynote 2: The Chip-Multiprocessing Paradigm Shift: Opportunities and Challenges

Software Defined Radio - A High Performance Embedded Challenge

I Analysis and Evaluation Techniques

A Practical Method for Quickly Evaluating Program Optimizations

Efficient Sampling Startup for Sampled Processor Simulation

Enhancing Network Processor Simulation Speed with Statistical Input Sampling

II Novel Memory and Interconnect Architectures

Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems

Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation

Streaming Sparse Matrix Compression/Decompression

XAMM: A High-Performance Automatic Memory Management System with Memory-Constrained Designs

III Security Architecture

Memory-Centric Security Architecture

A Novel Batch Rekeying Processor Architecture for Secure Multicast Key Management

Arc3D: A 3D Obfuscation Architecture

IV Novel Compiler and Runtime Techniques

Dynamic Code Region (DCR) Based Program Phase Tracking and Prediction for Dynamic Optimizations

Induction Variable Analysis with Delayed Abstractions

Garbage Collection Hints

V DomainSpecificArchitectures

Exploiting a Computation Reuse Cache to Reduce Energy in Network Processors

Dynamic Evolution of Congestion Trees: Analysis and Impact on Switch Architecture

A Single (Unified) Shader GPU Microarchitecture for Embedded Systems

A Low-Power DSP-Enhanced 32-Bit EISC Processor.

Other Format:

Printed edition:

ISBN:

978-3-540-32272-6

9783540322726

Access Restriction:

Restricted for use by site license.