Digital logic testing and simulation / Alexander Miczo.

Format:

Book

Author/Creator:

Miczo, Alexander.

Language:

English

Subjects (All):

Digital electronics--Testing.

Digital electronics.

Physical Description:

1 online resource (697 p.)

Edition:

2nd ed.

Place of Publication:

Hoboken, NJ : Wiley-Interscience, c2003.

Language Note:

English

System Details:

text file

Summary:

Your road map for meeting today's digital testing challengesToday, digital logic devices are common in products that impact public safety, including applications in transportation and human implants. Accurate testing has become more critical to reliability, safety, and the bottom line. Yet, as digital systems become more ubiquitous and complex, the challenge of testing them has become more difficult. As one development group designing a RISC stated, ""the work required to . . . test a chip of this size approached the amount of effort required to design it."" A valued reference for near

Contents:

DIGITAL LOGIC TESTING AND SIMULATION; CONTENTS; Preface; 1 Introduction; 1.1 Introduction; 1.2 Quality; 1.3 The Test; 1.4 The Design Process; 1.5 Design Automation; 1.6 Estimating Yield; 1.7 Measuring Test Effectiveness; 1.8 The Economics of Test; 1.9 Case Studies; 1.9.1 The Effectiveness of Fault Simulation; 1.9.2 Evaluating Test Decisions; 1.10 Summary; Problems; References; 2 Simulation; 2.1 Introduction; 2.2 Background; 2.3 The Simulation Hierarchy; 2.4 The Logic Symbols; 2.5 Sequential Circuit Behavior; 2.6 The Compiled Simulator; 2.6.1 Ternary Simulation

2.6.2 Sequential Circuit Simulation2.6.3 Timing Considerations; 2.6.4 Hazards; 2.6.5 Hazard Detection; 2.7 Event-Driven Simulation; 2.7.1 Zero-Delay Simulation; 2.7.2 Unit-Delay Simulation; 2.7.3 Nominal-Delay Simulation; 2.8 Multiple-Valued Simulation; 2.9 Implementing the Nominal-Delay Simulator; 2.9.1 The Scheduler; 2.9.2 The Descriptor Cell; 2.9.3 Evaluation Techniques; 2.9.4 Race Detection in Nominal-Delay Simulation; 2.9.5 Min-Max Timing; 2.10 Switch-Level Simulation; 2.11 Binary Decision Diagrams; 2.11.1 Introduction; 2.11.2 The Reduce Operation; 2.11.3 The Apply Operation

2.12 Cycle Simulation2.13 Timing Verification; 2.13.1 Path Enumeration; 2.13.2 Block-Oriented Analysis; 2.14 Summary; Problems; References; 3 Fault Simulation; 3.1 Introduction; 3.2 Approaches to Testing; 3.3 Analysis of a Faulted Circuit; 3.3.1 Analysis at the Component Level; 3.3.2 Gate-Level Symbols; 3.3.3 Analysis at the Gate Level; 3.4 The Stuck-At Fault Model; 3.4.1 The AND Gate Fault Model; 3.4.2 The OR Gate Fault Model; 3.4.3 The Inverter Fault Model; 3.4.4 The Tri-State Fault Model; 3.4.5 Fault Equivalence and Dominance; 3.5 The Fault Simulator: An Overview

3.6 Parallel Fault Processing3.6.1 Parallel Fault Simulation; 3.6.2 Performance Enhancements; 3.6.3 Parallel Pattern Single Fault Propagation; 3.7 Concurrent Fault Simulation; 3.7.1 An Example of Concurrent Simulation; 3.7.2 The Concurrent Fault Simulation Algorithm; 3.7.3 Concurrent Fault Simulation: Further Considerations; 3.8 Delay Fault Simulation; 3.9 Differential Fault Simulation; 3.10 Deductive Fault Simulation; 3.11 Statistical Fault Analysis; 3.12 Fault Simulation Performance; 3.13 Summary; Problems; References; 4 Automatic Test Pattern Generation; 4.1 Introduction

4.2 The Sensitized Path4.2.1 The Sensitized Path: An Example; 4.2.2 Analysis of the Sensitized Path Method; 4.3 The D-Algorithm; 4.3.1 The D-Algorithm: An Analysis; 4.3.2 The Primitive D-Cubes of Failure; 4.3.3 Propagation D-Cubes; 4.3.4 Justification and Implication; 4.3.5 The D-Intersection; 4.4 Testdetect; 4.5 The Subscripted D-Algorithm; 4.6 PODEM; 4.7 FAN; 4.8 Socrates; 4.9 The Critical Path; 4.10 Critical Path Tracing; 4.11 Boolean Differences; 4.12 Boolean Satisfiability; 4.13 Using BDDs for ATPG; 4.13.1 The BDD XOR Operation; 4.13.2 Faulting the BDD Graph; 4.14 Summary; Problems

References

Notes:

Description based upon print version of record.

Includes bibliographical references and index.

ISBN:

9786610366101

9781280366109

1280366109

9780470357125

0470357126

9780471457770

0471457779

9780471457787

0471457787

OCLC:

85819930