The system designer's guide to VHDL-AMS : analog, mixed-signal, and mixed-technology modeling / Peter J. Ashenden, Gregory D. Peterson, Darrell A. Teegarden.

Format:

Book

Author/Creator:

Ashenden, Peter J.

Contributor:

Peterson, Gregory D.

Teegarden, Darrell A.

Series:

Morgan Kaufmann series in systems on silicon.

Morgan Kaufmann series in systems on silicon

Language:

English

Subjects (All):

Electronic digital computers--Computer simulation.

Electronic digital computers.

VHDL (Computer hardware description language).

Physical Description:

1 online resource (909 p.)

Edition:

1st edition

Place of Publication:

San Francisco, Calif. : Morgan Kaufmann, c2003.

Language Note:

English

System Details:

text file

Summary:

The demand is exploding for complete, integrated systems that sense, process, manipulate, and control complex entities such as sound, images, text, motion, and environmental conditions. These systems, from hand-held devices to automotive sub-systems to aerospace vehicles, employ electronics to manage and adapt to a world that is, predominantly, neither digital nor electronic. To respond to this design challenge, the industry has developed and standardized VHDL-AMS, a unified design language for modeling digital, analog, mixed-signal, and mixed-technology systems. VHDL-AMS ext

Contents:

Front Cover; The System Designer's Guide to VHDL-AMS:Analog, Mixed-Signal, and Mixed-Technology Modeling; Copyright Page; Contents; Preface; Chapter 1. Fundamental Concepts; 1.1 Modeling Systems; 1.2 Domains and Levels of Modeling; 1.3 Modeling Languages; 1.4 VHDL-AMS Modeling Concepts; 1.5 Learning a New Language: Lexical Elements and Syntax; Exercises; Chapter 2. Scalar Data Types, Natures and Operations; 2.1 Constants and Variables; 2.2 Scalar Types; 2.3 Type Classification; 2.4 Scalar Natures; 2.5 Attributes of Scalar Types and Natures; 2.6 Expressions and Operators; Exercises

Chapter 3. Sequential Statements3.1 If Statements; 3.2 Case Statements; 3.3 Null Statements; 3.4 Loop Statements; 3.5 Assertion and Report Statements; Exercises; Chapter 4. Composite Data Types and Operations; 4.1 Arrays; 4.2 Unconstrained Arrays; 4.3 Array Operations and Referencing; 4.4 Records; Exercises; Chapter 5. Digital Modeling Constructs; 5.1 Entity Declarations; 5.2 Architecture Bodies; 5.3 Digital Behavioral Descriptions; 5.4 Digital Structural Descriptions; Exercises; Chapter 6. Analog Modeling Constructs; 6.1 Free Quantities; 6.2 Terminals and Branch Quantities

6.3 Attributes of Terminals and Quantities6.4 Simultaneous Statements; 6.5 Analog Structural Descriptions; 6.6 Discontinuities and Break Statements; 6.7 Step Limit Specifications; 6.8 Mixed-Signal Descriptions; 6.9 Mixed-Technology Descriptions; Exercises; Chapter 7. Design Processing; 7.1 Analysis; 7.2 Elaboration; 7.3 Execution; Exercises; Chapter 8. Case Study 1: Mixed-Signal Focus; 8.1 System Overview; 8.2 Command and Control System Design; 8.3 Design Trade-Off Analysis; Exercises; Chapter 9. Subprograms; 9.1 Procedures; 9.2 Procedure Parameters; 9.3 Concurrent Procedure Call Statements

9.4 Functions9.5 Simultaneous Procedural Statements; 9.6 Overloading; 9.7 Visibility of Declarations; Exercises; Chapter 10. Packages and Use Clauses; 10.1 Package Declarations; 10.2 Package Bodies; 10.3 Use Clauses; 10.4 The Predefined Package Standard; 10.5 IEEE Standard Packages; Exercises; Chapter 11. Aliases; 11.1 Aliases for Data Objects; 11.2 Aliases for Non-Data Items; Exercises; Chapter 12. Generic Constants; 12.1 Parameterizing Behavior; 12.2 Parameterizing Structure; Exercises; Chapter 13. Frequency and Transfer Function Modeling; 13.1 Frequency-Based Modeling; 13.2 Noise Modeling

13.3 Laplace Transfer Functions13.4 Discrete Transfer Functions and Sampling; Exercises; Chapter 14. Case Study 2: Mixed-Technology Focus; 14.1 Rudder System Overview; 14.2 S-Domain Implementation; 14.3 Mixed Mechanical/S-Domain Implementation; 14.4 Design Trade-Off Analysis; Exercises; Chapter 15. Resolved Signals; 15.1 Basic Resolved Signals; 15.2 IEEE Std_Logic_1164 Resolved Subtypes; 15.3 Resolved Signals and Ports; 15.4 Resolved Signal Parameters; Exercises; Chapter 16. Components and Configurations; 16.1 Components; 16.2 Configuring Component Instances; 16.3 Configuration Specifications

Exercises

Notes:

Description based upon print version of record.

Includes bibliographical references (p. 853-855) and index.

ISBN:

9786611754969

9781281754967

128175496X

9780080518367

0080518362

OCLC:

437246469