Analog integrated circuit design

Format:

Book

Author/Creator:

Carusone, Tony Chan, Author.

Contributor:

Martin, Kenneth W, Contributor.

Johns, David, Contributor.

Language:

English

Subjects (All):

Linear integrated circuits--Design and construction.

Linear integrated circuits.

Analog electronic systems--Design.

Analog electronic systems.

Electronic circuit design.

Physical Description:

1 online resource (1 v.) : ill.

Edition:

2nd ed.

Place of Publication:

[Place of publication not identified] John Wiley & Sons 2012

Language Note:

English

System Details:

text file

Summary:

The 2nd Edition of Analog Integrated Circuit Design focuses on more coverage about several types of circuits that have increased in importance in the past decade. Furthermore, the text is enhanced with material on CMOS IC device modeling, updated processing layout and expanded coverage to reflect technical innovations. CMOS devices and circuits have more influence in this edition as well as a reduced amount of text on BiCMOS and bipolar information. New chapters include topics on frequency response of analog ICs and basic theory of feedback amplifiers.

Contents:

Intro

Copyright

Preface

Contents

Chapter 1: Integrated-Circuit Devices and Modelling

1.1: Semiconductors and pn Junctions

1.1.1: Diodes

1.1.2: Reverse-Biased Diodes

1.1.3: Graded Junctions

1.1.4: Large-Signal Junction Capacitance

1.1.5: Forward-Biased Junctions

1.1.6: Junction Capacitance of Forward-Biased Diode

1.1.7: Small-Signal Model of a Forward-Biased Diode

1.1.8: Schottky Diodes

1.2: MOS Transistors

1.2.1: Symbols for MOS Transistors

1.2.2: Basic Operation

1.2.3: Large-Signal Modelling

1.2.4: Body Effect

1.2.5: p-Channel Transistors

1.2.6: Low-Frequency Small-Signal Modelling in the Active Region

1.2.7: High-Frequency Small-Signal Modelling in the Active Region

1.2.8: Small-Signal Modelling in the Triode and Cutoff Regions

1.2.9: Analog Figures of Merit and Trade-offs

1.3: Device Model Summary

1.3.1: Constants

1.3.2: Diode Equations

1.3.3: MOS Transistor Equations

1.4: Advanced MOS Modelling

1.4.1: Subthreshold Operation

1.4.2: Mobility Degradation

1.4.3: Summary of Subthreshold and Mobility Degradation Equations

1.4.4: Parasitic Resistances

1.4.5: Short-Channel Effects

1.4.6: Leakage Currents

1.5: SPICE Modelling Parameters

1.5.1: Diode Model

1.5.2: MOS Transistors

1.5.3: Advanced SPICE Models of MOS Transistors

1.6: Passive Devices

1.6.1: Resistors

1.6.2: Capacitors

1.7: Appendix

1.7.1: Diode Exponential Relationship

1.7.2: Diode-Diffusion Capacitance

1.7.3: MOS Threshold Voltage and the Body Effect

1.7.4: MOS Triode Relationship

1.8: Key Points

1.9: References

1.10: Problems

Chapter 2: Processing and Layout

2.1: CMOS Processing

2.1.1: The Silicon Wafer

2.1.2: Photolithography and Well Definition

2.1.3: Diffusion and Ion Implantation.

2.1.4: Chemical Vapor Deposition and Defining the Active Regions

2.1.5: Transistor Isolation

2.1.6: Gate-Oxide and Threshold-Voltage Adjustments

2.1.7: Polysilicon Gate Formation

2.1.8: Implanting the Junctions, Depositing SiO2, and Opening Contact Holes

2.1.9: Annealing, Depositing and Patterning Metal, and Overglass Deposition

2.1.10: Additional Processing Steps

2.2: CMOS Layout and Design Rules

2.2.1: Spacing Rules

2.2.2: Planarity and Fill Requirements

2.2.3: Antenna Rules

2.2.4: Latch-Up

2.3: Variability and Mismatch

2.3.1: Systematic Variations Including Proximity Effects

2.3.2: Process Variations

2.3.3: Random Variations and Mismatch

2.4: Analog Layout Considerations

2.4.1: Transistor Layouts

2.4.2: Capacitor Matching

2.4.3: Resistor Layout

2.4.4: Noise Considerations

2.5: Key Points

2.6: References

2.7: Problems

Chapter 3: Basic Current Mirrors and Single-Stage Amplifiers

3.1: Simple CMOS Current Mirror

3.2: Common-Source Amplifier

3.3: Source-Follower or Common-Drain Amplifier

3.4: Common-Gate Amplifier

3.5: Source-Degenerated Current Mirrors

3.6: Cascode Current Mirrors

3.7: Cascode Gain Stage

3.8: MOS Differential Pair and Gain Stage

3.9: Key Points

3.10: References

3.11: Problems

Chapter 4: Frequency Response of Electronic Circuits

4.1: Frequency Response of Linear Systems

4.1.1: Magnitude and Phase Response

4.1.2: First-Order Circuits

4.1.3: Second-Order Low-Pass Transfer Functions with Real Poles

4.1.4: Bode Plots

4.1.5: Second-Order Low-Pass Transfer Functions with Complex Poles

4.2: Frequency Response of Elementary Transistor Circuits

4.2.1: High-Frequency MOS Small-Signal Model

4.2.2: Common-Source Amplifier

4.2.3: Miller Theorem and Miller Effect

4.2.4: Zero-Value Time-Constant Analysis.

4.2.5: Common-Source Design Examples

4.2.6: Common-Gate Amplifier

4.3: Cascode Gain Stage

4.4: Source-Follower Amplifier

4.5: Differential Pair

4.5.1: High-Frequency T-Model

4.5.2: Symmetric Differential Amplifier

4.5.3: Single-Ended Differential Amplifier

4.5.4: Differential Pair with Active Load

4.6: Key Points

4.7: References

4.8: Problems

Chapter 5: Feedback Amplifiers

5.1: Ideal Model of Negative Feedback

5.1.1: Basic Definitions

5.1.2: Gain Sensitivity

5.1.3: Bandwidth

5.1.4: Linearity

5.1.5: Summary

5.2: Dynamic Response of Feedback Amplifiers

5.2.1: Stability Criteria

5.2.2: Phase Margin

5.3: First-and Second-Order Feedback Systems

5.3.1: First-Order Feedback Systems

5.3.2: Second-Order Feedback Systems

5.3.3: Higher-Order Feedback Systems

5.4: Common Feedback Amplifiers

5.4.1: Obtaining the Loop Gain, L(s)

5.4.2: Non-Inverting Amplifier

5.4.3: Transimpedance (Inverting) Amplifiers

5.5: Summary of Key Points

5.6: References

5.7: Problems

Chapter 6: Basic Opamp Design and Compensation

6.1: Two-Stage CMOS Opamp

6.1.1: Opamp Gain

6.1.2: Frequency Response

6.1.3: Slew Rate

6.1.4: n-Channel or p-Channel Input Stage

6.1.5: Systematic Offset Voltage

6.2: Opamp Compensation

6.2.1: Dominant-Pole Compensation and Lead Compensation

6.2.2: Compensating the Two-Stage Opamp

6.2.3: Making Compensation Independent of Process and Temperature

6.3: Advanced Current Mirrors

6.3.1: Wide-Swing Current Mirrors

6.3.2: Enhanced Output-Impedance Current Mirrors and Gain Boosting

6.3.3: Wide-Swing Current Mirror with Enhanced Output Impedance

6.3.4: Current-Mirror Symbol

6.4: Folded-Cascode Opamp

6.4.1: Small-Signal Analysis

6.4.2: Slew Rate

6.5: Current Mirror Opamp

6.6: Linear Settling Time Revisited.

6.7: Fully Differential Opamps

6.7.1: Fully Differential Folded-Cascode Opamp

6.7.2: Alternative Fully Differential Opamps

6.7.3: Low Supply Voltage Opamps

6.8: Common-Mode Feedback Circuits

6.9: Summary of Key Points

6.10: References

6.11: Problems

Chapter 7: Biasing, References, and Regulators

7.1: Analog Integrated Circuit Biasing

7.1.1: Bias Circuits

7.1.2: Reference Circuits

7.1.3: Regulator Circuits

7.2: Establishing Constant Transconductance

7.2.1: Basic Constant-Transconductance Circuit

7.2.2: Improved Constant-Transconductance Circuits

7.3: Establishing Constant Voltages and Currents

7.3.1: Bandgap Voltage Reference Basics

7.3.2: Circuits for Bandgap References

7.3.3: Low-Voltage Bandgap Reference

7.3.4: Current Reference

7.4: Voltage Regulation

7.4.1: Regulator Specifications

7.4.2: Feedback Analysis

7.4.3: Low Dropout Regulators

7.5: Summary of Key Points

7.6: References

7.7: Problems

Chapter 8: Bipolar Devices and Circuits

8.1: Bipolar-Junction Transistors

8.1.1: Basic Operation

8.1.2: Analog Figures of Merit

8.2: Bipolar Device Model Summary

8.3: SPICE Modeling

8.4: Bipolar and BICMOS Processing

8.4.1: Bipolar Processing

8.4.2: Modern SiGe BiCMOS HBT Processing

8.4.3: Mismatch in Bipolar Devices

8.5: Bipolar Current Mirrors and Gain Stages

8.5.1: Current Mirrors

8.5.2: Emitter Follower

8.5.3: Bipolar Differential Pair

8.6: Appendix

8.6.1: Bipolar Transistor Exponential Relationship

8.6.2: Base Charge Storage of an Active BJT

8.7: Summary of Key Points

8.8: References

8.9: Problems

Chapter 9: Noise and Linearity Analysis and Modelling

9.1: Time-Domain Analysis

9.1.1: Root Mean Square (rms) Value

9.1.2: SNR

9.1.3: Units of dBm

9.1.4: Noise Summation

9.2: Frequency-Domain Analysis.

9.2.1: Noise Spectral Density

9.2.2: White Noise

9.2.3: 1/f, or Flicker, Noise

9.2.4: Filtered Noise

9.2.5: Noise Bandwidth

9.2.6: Piecewise Integration of Noise

9.2.7: 1/f Noise Tangent Principle

9.3: Noise Models for Circuit Elements

9.3.1: Resistors

9.3.2: Diodes

9.3.3: Bipolar Transistors

9.3.4: MOSFETS

9.3.5: Opamps

9.3.6: Capacitors and Inductors

9.3.7: Sampled Signal Noise

9.3.8: Input-Referred Noise

9.4: Noise Analysis Examples

9.4.1: Opamp Example

9.4.2: Bipolar Common-Emitter Example

9.4.3: CMOS Differential Pair Example

9.4.4: Fiber-Optic Transimpedance Amplifier Example

9.5: Dynamic Range Performance

9.5.1: Total Harmonic Distortion (THD)

9.5.2: Third-Order Intercept Point (IP3)

9.5.3: Spurious-Free Dynamic Range (SFDR)

9.5.4: Signal-to-Noise and Distortion Ratio (SNDR)

9.6: Key Points

9.7: References

9.8: Problems

Chapter 10: Comparators

10.1: Comparator Specifications

10.1.1: Input Offset and Noise

10.1.2: Hysteresis

10.2: Using an Opamp for a Comparator

10.2.1: Input-Offset Voltage Errors

10.3: Charge-Injection Errors

10.3.1: Making Charge-Injection Signal Independent

10.3.2: Minimizing Errors Due to Charge-Injection

10.3.3: Speed of Multi-Stage Comparators

10.4: Latched Comparators

10.4.1: Latch-Mode Time Constant

10.4.2: Latch Offset

10.5: Examples of CMOS and BiCMOS Comparators

10.5.1: Input-Transistor Charge Trapping

10.6: Examples of Bipolar Comparators

10.7: Key Points

10.8: References

10.9: Problems

Chapter 11: Sample-and-Hold and Translinear Circuits

11.1: Performance of Sample-and-Hold Circuits

11.1.1: Testing Sample and Holds

11.2: MOS Sample-and-Hold Basics

11.3: Examples of CMOS S/H Circuits

11.4: Bipolar and BiCMOS Sample-and-Holds

11.5: Translinear Gain Cell.

11.6: Translinear Multiplier.

Notes:

Bibliographic Level Mode of Issuance: Monograph

Includes bibliographical references and index.

ISBN:

1-118-21373-4

OCLC:

864831329