My Account Log in

1 option

Real world multicore embedded systems : a practical approach / Bryon Moyer.

O'Reilly Online Learning: Academic/Public Library Edition Available online

View online
Format:
Book
Author/Creator:
Moyer, Bryon.
Contributor:
Moyer, Bryon.
Series:
Expert guide series.
Expert guide Real world multicore embedded systems
Language:
English
Subjects (All):
Embedded computer systems.
Multiprocessors.
Physical Description:
1 online resource (xxii, 623 pages) : illustrations (some color).
Edition:
1st edition
Place of Publication:
Oxford : Newnes, 2013.
Language Note:
English
System Details:
text file
Summary:
This Expert Guide gives you the techniques and technologies in embedded multicore to optimally design and implement your embedded system. Written by experts with a solutions focus, this encyclopedic reference gives you an indispensable aid to tackling the day-to-day problems when building and managing multicore embedded systems. Following an embedded system design path from start to finish, our team of experts takes you from architecture, through hardware implementation to software programming and debug. With this book you will learn: What motivates multicor
Contents:
Front Cover; Real World Multicore Embedded Systems; Copyright Page; Contents; About the Editor; About the Authors; 1 Introduction and Roadmap; Multicore is here; Scope; Who should read this book?; Organization and roadmap; Concurrency; Architecture; High-level architecture; Memory architecture; Interconnect; Infrastructure; Operating systems; Virtualization; Multicore-related libraries; Application software; Languages and tools; Partitioning applications; Synchronization; Hardware assistance; Hardware accelerators; Synchronization hardware; System-level considerations; Bare-metal systems
DebugA roadmap of this book; 2 The Promise and Challenges of Concurrency; Concurrency fundamentals; Two kinds of concurrency; Data parallelism; Functional parallelism; Dependencies; Producers and consumers of data; Loops and dependencies; Shared resources; Summary; 3 Multicore Architectures; The need for multicore architectures; Multicore architecture drivers; Traditional sequential software paradigms break; Scope of multicore hardware architectures; Basic multicore hardware architecture overview; Specific multicore architecture characteristics; Processing architectures
ALU processing architecturesLightweight processing architectures; Mediumweight processing architectures; Heavyweight processing architectures; Communication architectures; Memory architectures; Application specificity; Application-specific platform topologies; Integration of multicore systems, MPSoCs and sub-systems; Programming challenges; Application characteristics; MPSoC analysis, debug and verification; Shortcomings and solutions; MPSoC parallel programming; Parallel software and MPSoCs; Summary; References; 4 Memory Models for Embedded Multicore Architecture; Introduction; Memory types
RAMDRAM; SRAM; NVRAM; DPRAM; EPROM; Flash; SD-MMC; Hard Disk; Memory architecture; Cache; Translation lookaside buffer (TLB); Instruction cache; Data cache; Cache customization; Virtual memory; Scratch pad; Software overlays; DMA; DRAM; Special-purpose memory; Memory structure of multicore architecture; Shared memory architecture; Uniform memory access (UMA); Non-uniform memory access (NUMA); Distributed memory architecture; Cache memory in multicore chips; Cache coherency; Directory-based cache coherence protocol; Snoopy cache coherence protocol; MESI cache coherence protocol
Cache-related performance issuesFalse sharing and the ping-pong effect; Processor affinity; Cache locking; Transactional memory; Software transactional memory; Hardware transactional memory; Hybrid transactional memory; Summary; References; 5 Design Considerations for Multicore SoC Interconnections; Introduction; Importance of interconnections in an SoC; Terminology; Organization of the chapter; Communication activity in multicore SoCs; Transaction-based communication; Storage-oriented transactions; Addressed Accesses; Non-addressed storage-oriented transactions; Messages; Interrupts
Concurrency of communication and segregation of traffic
Notes:
Description based upon print version of record.
Includes bibliographical references and index.
ISBN:
9781299261815
1299261817
9780123914613
0123914612
OCLC:
834587505

The Penn Libraries is committed to describing library materials using current, accurate, and responsible language. If you discover outdated or inaccurate language, please fill out this feedback form to report it and suggest alternative language.

Find

Home Release notes

My Account

Shelf Request an item Bookmarks Fines and fees Settings

Guides

Using the Find catalog Using Articles+ Using your account