FPGAs / Clive "Max" Maxfield [editor] ; with W. Bolton ... [et al.].

Format:

Book

Contributor:

Maxfield, Clive, 1957-

Series:

World class designs.

Newnes world class designs series

Language:

English

Subjects (All):

Field programmable gate arrays.

Field programmable gate arrays--Design and construction.

Physical Description:

1 online resource (527 p.)

Edition:

1st edition

Other Title:

Field programmable gate arrays

Place of Publication:

Amsterdam ; Boston : Newnes/Elsevier, c2009.

Language Note:

English

System Details:

text file

Summary:

All the design and development inspiration and direction a harware engineer needs in one blockbuster book! Clive ""Max"" Maxfield renowned author, columnist, and editor of PL DesignLine has selected the very best FPGA design material from the Newnes portfolio and has compiled it into this volume. The result is a book covering the gamut of FPGA design from design fundamentals to optimized layout techniques with a strong pragmatic emphasis. In addition to specific design techniques and practices, this book also discusses various approaches to solving FPGA design problems and how to successfully

Contents:

Front Cover; FPGAs World Class Designs; Copyright Page; Contents; Preface; About the Editor; About the Contributors; Chapter 1: Alternative FPGA Architectures; 1.1 A Word of Warning; 1.3 Antifuse versus SRAM versus; 1.4 Fine-, Medium-, and Coarse-Grained Architectures; 1.11 Clock Trees and Clock Managers; 1.15 System Gates versus Real Gates; 1.16 FPGA Years; Chapter 2: Design Techniques, Rules, and Guidelines; 2.1 Hardware Description Languages; 2.2 Top-Down Design; 2.3 Synchronous Design; 2.5 Bus Contention; 2.8 Testing Redundant Logic; 2.10 Observable Nodes; 2.11 Scan Techniques

2.14 SummaryChapter 3: A VHDL Primer: The Essentials; 3.1 Introduction; 3.4 Process: Basic Functional Unit in VHDL; 3.7 Hierarchical Design; 3.8 Debugging Models; Chapter 4: Modeling Memories; 4.2 Modeling Memory Functionality; 4.3 VITAL_Memory Path Delays; 4.4 VITAL_Memory Timing Constraints; Chapter 5: Introduction to Synchronous State Machine Design and Analysis; 5.1 Introduction; 5.3 The Fully Documented State Diagram; 5.5 Introduction to Flip-Flops; 5.6 Procedure for FSM (Flip-Flop) Design and the Mapping Algorithm; 5.7 The D Flip-Flops: General

5.8 Flip-Flop Conversion: The T, JK Flip-Flops and Miscellaneous Flip-Flops5.11 Setup and Hold Time Requirements of Flip-Flops; 5.13 Analysis of Simple State Machines; References; Chapter 6: Embedded Processors; 6.1 Introduction; 6.4 Summary; Chapter 7: Digital Signal Processing; 7.1 Overview; 7.2 Basic DSP System; 7.5 Parallel Execution in DSP Components; Chapter 8: Basics of Embedded Audio Processing; 8.1 Introduction; References; Chapter 9: Basics of Embedded Video and Image Processing; 9.1 Introduction; 9.4 Digital Video

Chapter 10: Programming Streaming FPGA Applications Using Block Diagrams in Simulink10.1 Designing High-Performance Datapaths using Stream-Based Operators; 10.2 An Image-Processing Design Driver; References; Chapter 11: Ladder and Functional Block Programming; 11.1 Ladder Diagrams; 11.4 Multiple Outputs; 11.6 Function Blocks; 11.7 Program Examples; Chapter 12: Timers; 12.1 Types of Timers; Index

Notes:

Description based upon print version of record.

Includes bibliographical references and index.

ISBN:

9786612169380

9781282169388

1282169386

9780080950808

0080950809

OCLC:

476274697