2017 Euromicro Conference on Digital System Design (DSD) : proceedings : 30 August-1 September 2017, Vienna, Austria / Hana Kubatova,editor.

Format:

Book

Contributor:

Kubatova, Hana, editor.

Language:

English

Subjects (All):

Computer architecture--Congresses.

Computer architecture.

Physical Description:

1 online resource (xxviii, 556 pages) : illustrations

Other Title:

2017 Euromicro Conference on Digital System Design

Place of Publication:

Piscataway : IEEE, 2017.

Summary:

The Euromicro Conference on Digital System Design (DSD) addresses all aspects of (embedded, pervasive and high performance) digital and mixed HW SW system engineering, covering the whole design trajectory from specification down to micro architectures, digital circuits and VLSI implementations It is a forum for researchers and engineers from academia and industry working on advanced investigations, developments and applications. It focuses on today's and future challenges of advanced embedded, high performance and cyber physical applications system and processor architectures for embedded and high performance HW SW systems design methodology and design automation for all design levels of embedded, high performance and cyber physical systems modern implementation technologies from full custom in nanometer technology nodes, through FPGAs, to MPSoC infrastructures.

Contents:

Building a Better Random Number Generator for Stochastic Computing,"

Rapid Estimation of Power-Management Unit Overhead from System-Level Specification,"

Loop Overhead Reduction Techniques for Coarse Grained Reconfigurable Architectures,"

Autonomous Power Management for Embedded Systems Using a Non-linear Power Predictor,"

An Aspect and Transaction Oriented Programming, Design and Verification Language (PDVL),"

Optimizing Memory Access Performance Using Hardware Assisted Virtualization in Retargetable Dynamic Binary Translation,"

Static Write Buffer Cache Modeling to Increase Host-Compiled Simulation Accuracy,"

Assertion-Based Verification for SoC Models and Identification of Key Events,"

An Architecture for Online-Diagnosis Systems Supporting Compressed Communication,"

A Hardware/Software Codesign for the Chemical Reactivity of BRAMS,"

Nepteron Processor for Real-Time Computation of Conductance-Based Neuronal Networks,"

System-Aware Performance Monitoring Unit for RISC-V Architectures,"

SPEED: Open-Source Framework to Accelerate Speech Recognition on Embedded GPUs,"

EventIRQ: An Event Based and Priority Aware IRQ Handling for Multi-tasking Environments,"

Design of an On-chip System for the SET Pulse Width Measurement,"

Acceleration Techniques for System-Hyper-Pipelined Soft-Processors on FPGAs,"

Application Specific Behavioral Synthesis Design Space Exploration: Artificial Neural Networks. A Case Study,"

Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis,"

Performance Targeted Minimization of Incompletely Specified Finite State Machines for Implementation in FPGA Devices,"

A Feedback-Based Design Space Exploration Subsystem for the Automation of Architectures Synthesis on Proprietary FPGA Toolchains,"

Analysis and Visualization of Product Memory Layout in IP-XACT,"

SAT-Based Generation of Optimum Function Implementations with XOR Gates,"

Scalable and Power-Efficient Implementation of an Asynchronous Router with Buffer Sharing,"

Packet Classification with Limited Memory Resources,"

A Distributed NUCA Architecture Using an Efficient NoC Multicasting Support,"

A Programmable Inbound Transfer Processor for Active Messages in Embedded Multicore Systems,"

Automatic Control Flow Generation for OpenVX Graphs,"

Higher-Order Side-Channel Protected Implementations of KECCAK,"

Lightweight Software Encryption for Embedded Processors,"

A Design Strategy for Digit Serial Multiplier Based Binary Edwards Curve Scalar Multiplier Architectures,"

Hardware-Secured Configuration and Two-Layer Attestation Architecture for Smart Sensors,"

Side Channel Evaluation of PUF-Based Pseudorandom Permutation,"

How Microprobing Can Attack Encrypted Memory,"

Role of Laser-Induced IR Drops in the Occurrence of Faults: Assessment and Simulation,"

Influence of Fault-Tolerance Techniques on Power-Analysis Resistance of Cryptographic Design,"

Thermal Sensor Based Hardware Trojan Detection in FPGAs,"

Analysis and Inner-Round Pipelined Implementation of Selected Parallelizable CAESAR Competition Candidates,"

Counterfeit IC Detection By Image Texture Analysis,"

Run-Time Effect by Inserting Hardware Trojans, in Combinational Circuits,"

Exploiting Quantum Gates in Secure Computation,"

IoT Components LifeCycle Based Security Analysis,"

Necessity of Fault Tolerance Techniques in Xilinx Kintex 7 FPGA Devices for Space Missions: A Case Study,"

SAT-Based ATPG for Zero-Aliasing Compaction,"

A Functional Test Framework to Observe MPSoC Power Management Techniques in Virtual Platforms,"

PCG: Partially Clock-Gating Approach to Reduce the Power Consumption of Fault-Tolerant Register Files,"

Setup for an Experimental Study of Radiation Effects in 65nm CMOS,"

Reliability Analysis and Improvement of FPGA-Based Robot Controller,"

Thermal Effect on Performance, Power, and BTI Aging in FinFET-Based Designs,"

On Dependability Assessment of Fault Tolerant Systems by Means of Statistical Model Checking,"

A Probabilistic Context-Free Grammar Based Random Test Program Generation,"O.

Dependability Prediction Involving Temporal Redundancy and the Effect of Transient Faults,"

LORAP: Low-Overhead Power and Reliability-Aware Task Mapping Based on Instruction Footprint for Real-Time Applications,"

A 3D Time-of-Flight Mixed-Criticality System for Environment Perception,"

A Subplatooning Strategy for Safe Braking Maneuvers,"

On the Benefits of Multicores for Real-Time Systems,"

FPGA-Centric High Performance Embedded Computing: Challenges and Trends,"R.

A Survey on Open-Source Flight Control Platforms of Unmanned Aerial Vehicle,"E.

A Scalable Cloud Computing Infrastructure for Geospatial Data Analytics for Change Detection,"R.

Evaluating the Impact of Communication Network Performance on Supervisory Supermarket Control,"J.

Modular Development and Certification of Dependable Mixed-Criticality Systems,"A.

Mixed Time-Criticality Process Interferences Characterization on a Multicore Linux System,"

Model-Based Function Mapping and Bandwidth Reservation for Mixed-Critical Adaptive Systems,"

Boosting Guaranteed Performance in Wormhole NoCs with Probabilistic Timing Analysis,"

The HELICoiD Project: Parallel SVM for Brain Cancer Classification,"

Hardware Platforms Benchmark For Real-Time Polyp Detection,"

Wireless and Portable System for the Study of in-vitro Cell Culture Impedance Spectrum by Electrical Impedance Spectroscopy,"

Towards a Mobile Health Platform with Parallel Processing and Multi-sensor Capabilities,"

Towards a Safe Software Development Environment,"

MANGO: Exploring Manycore Architectures for Next-GeneratiOn HPC Systems,"

Paving the Way Towards a Highly Energy-Efficient and Highly Integrated Compute Node for the Exascale Revolution: The ExaNoDe Approach,"A.

The MegaM@Rt2 ECSEL Project: MegaModelling at Runtime Scalable Model-Based Framework for Continuous Development and Runtime Validation of Complex Systems,"W.

Security & Trusted Devices in the Context of Internet of Things (IoT),"

The Next Generation of Exascale-Class Systems: The ExaNeSt Project,"

Exploiting Kant and Kimuraas Matrix Inversion Algorithm on FPGA,"

Designing a Synthetic Aperture Radara Data Formatting and Antenna Gyro Stabilizing Module,"

Two-Phase Interarrival Time Prediction for Runtime Resource Management,"

Low-Cost Sub-5W Processors for Edge HPC,"P.

A Methodology for Predicting Application-Specific Achievable Memory Bandwidth for HW/SW-Codesign,"

Adaptive Reliability for Fault Tolerant Multicore Systems,"I.

High-Performance General-Purpose Arithmetic Operations Using the Massive Parallel DNA-Based Computation,"

Optimal Placement of Heterogeneous Uncore Component in 3D Chip-Multiprocessors,".

Notes:

Description based on publisher supplied metadata and other sources.

ISBN:

1-5386-2146-0