Advanced nanoelectronics : post-silicon materials and devices / edited by Muhammad Mustafa Hussain.

Format:

Book

Contributor:

Hussain, Muhammad Mustafa, editor.

Language:

English

Subjects (All):

Nanoelectronics.

Physical Description:

xii, 272 pages : illustrations ; 24 cm

Place of Publication:

Weinheim : Wiley-VCH, 2018.

Contents:

1 The Future of CMOS: More Moore or a New Disruptive Technology? p. 1 / Nazek El-Atab and Muhammad M. Hussain

1.1 FinFET Technology p. 2

1.1.1 State-of-the-Art FinFETs p. 3

1.1.1.1 FinFET with Si Channel p. 3

1.1.1.2 FinFET with High-Mobility Material Channel p. 4

1.1.1.3 FinFET with TMD Channel p. 5

1.1.1.4 SOI versus Bulk FinFET p. 5

1.1.2 Industrial State p. 6

1.1.3 Challenges and Limitations p. 7

1.2 3D Integrated Circuit Technology p. 8

1.2.1 Research State p. 9

1.2.1.1 Thermal Management p. 9

1.2.1.2 Through-silicon-vias p. 9

1.2.1.3 Bonding in 3D IC p. 10

1.2.1.4 Test and Yield p. 12

1.2.2 Industrial State p. 12

1.2.3 Challenges and Limitations p. 13

1.3 Neuromorphic Computing Technology p. 13

1.3.1 State-of-the-Art Nonvolatile Memory as a Synapse p. 14

1.3.1.1 Phase Change Memory p. 15

1.3.1.2 Conductive-Bridging RAM p. 16

1.3.1.3 Filamentary RRAM p. 17

1.3.2 Research Programs and Industrial State of Neuromorphic Computing p. 18

1.4 Quantum Computing Technology p. 19

1.4.1 Quantum Bit Requirement p. 20

1.4.2 Research State p. 20

1.4.2.1 Spin-Based Qubits p. 20

1.4.3 Superconducting Circuits for Quantum Information p. 21

1.4.4 Industry State p. 22

1.4.5 Challenges and Limitations to Quantum Computing p. 23

2 Nanowire Field-Effect Transistors p. 33 / Debarghya Sarkar and Ivan S. Esqueda and Rehan Kapadia

2.1 General Scaling Laws Leading to Nanowire Architectures p. 33

2.1.1 Scaling of Planar Devices and Off-state Leakage Current p. 33

2.1.2 FinFET and UTB Devices for Improved Electrostatics p. 35

2.1.3 Nanowires as the Ultimate Limit of Electrostatic Control p. 37

2.1 A Quantum Effects p. 39

2.1.5 Drive Current p. 43

2.2 Nanowire Growth and Device Fabrication Approaches p. 43

2.2.1 Bottom-up VLS Growth p. 43

2.2.2 Top-down Oxidation p. 45

2.3 State-of-the-Art Nanowire Devices p. 45

2.3.1 Silicon Devices p. 45

2.3.2 III-V Devices p. 46

3 Two-dimensional Materials for Electronic Applications p. 55 / Haimeng Zhang and Han Wang

3.1 2D Materials Transistor and Device Technology p. 56

3.1.1 Operation and Characteristics of 2D-Materials-Based FETs p. 57

3.1.2 Ambipolar Property of Graphene p. 57

3.1.3 Important Figures of Merit p. 58

3.1.3.1 Ion∕Ioff Ratio p. 58

3.1.3.2 Subthreshold Swing p. 59

3.1.3.3 Cutoff Frequency and Maximum Frequency of Oscillation p. 59

3.1.3.4 Minimum Noise Figure p. 60

3.1.4 Device Optimization p. 61

3.1.4.1 Mobility Engineering p. 61

3.1.4.2 Current Saturation p. 62

3.1.4.3 Metal Contact p. 63

3.2 Graphene Electronics for Radiofrequency Applications p. 64

3.2.1 Experimental Graphene RF Transistors p. 65

3.2.2 Graphene-Based Integrated Circuits p. 67

3.2.2.1 Graphene Ambipolar Devices p. 67

3.2.2.2 Graphene Oscillators p. 73

3.2.2.3 Graphene RF Receivers p. 73

3.2.2.4 Graphene Electromechanical Devices: Resonators and RF Switches p. 74

3.3 MoS2 Devices for Digital Application p. 76

3.3.1 Experimental MoS₂ Transistors p. 77

3.3.2 MoS₂-Based Integrated Circuits p. 78

3.3.2.1 Direct-Coupled FET Logic Circuits p. 78

3.3.2.2 Logic Gates p. 79

3.3.2.3 A Static Random Access Memory Cell based on MoS₂ p. 82

3.3.2.4 Ring Oscillators based on MoS₂ p. 82

3.3.2.5 Microprocessors based on MoS₂ p. 85

4 Integration of Germanium into Modern CMOS: Challenges and Breakthroughs p. 91 / Wonil Chung and Heng Wu and Peide D. Ye

4.2 Junction Formation for Germanium MOS Devices p. 92

4.2.1 Charge Neutrality Level and Fermi Level Pinning p. 92

4.2.2 Metal/Ge Contacts p. 93

4.2.2.1 Alleviation of FLP p. 93

4.2.2.2 Metal/n-Ge Contact p. 93

4.2.2.3 Recessed Contact Formation p. 94

4.3 Process Integration for Ge MOS Devices p. 97

4.3.1 Interface Engineering Issues p. 97

4.3.2 Various Gate Stack Combinations for Ge MOSFET p. 97

4.3.2.1 GeOx-Free Gate Stack with ALD High-K p. 98

4.3.2.2 Silicon Interfacial Layer Passivation p. 99

4.3.2.3 Germanium (Oxy)Nitridation p. 99

4.3.2.4 Ge02-Based Gate Stacks p. 99

4.3.2.5 Rare-Earth Oxides Integrated into Germanium MOSFETs p. 100

4.3.3 Stress and Relaxation of Ge Layer on an Si-Based Substrate p. 102

4.4 State-of-the-Art Ge CMOS with Recessed Channel and S/D p. 102

4.4.1 Germanium CMOS Devices p. 102

4.4.2 Germanium CMOS Circuits p. 105

4.5 Steep-Slope Device: NCFET p. 107

5 Carbon Nanotube Logic Technology p. 119 / Jianshi Tang and Shu-Jen Han

5.1 Introduction - Silicon CMOS Scaling and the Challenges p. 119

5.2 Fundamentals of Carbon Nanotube p. 122

5.3 Complementary Logic and Device Scalability Demonstrations p. 124

5.3.1 CNT NFET and Contact Engineering for CMOS Logic p. 124

5.3.2 Channel Length Scaling in CNTFET p. 127

5.3.3 Contact Length Scaling in CNTFET p. 132

5.4 Perspective of CNT-Based Logic Technology p. 138

5.4.1 CVD-Grown CNT versus Solution-Processed CNT p. 138

5.4.2 Purity and Placement of Solution-Processed CNTs p. 140

5.4.3 Variability in CNTFETs p. 140

5.4.4 Circuit-Level Integration p. 142

6 Tunnel Field-Effect Transistors p. 151 / Deblina Sarkar

6.2 Tunnel Field-Effect Transistors: The Fundamentals p. 153

6.2.1 Working Principle p. 153

6.2.2 Single-Carrier Tunneling Barrier and Subthreshold Swing p. 154

6.3 Modeling of TFETs p. 156

6.4 Design and Fabrication of TFETs p. 161

6.4.1 Design Considerations p. 161

6.4.2 Current Status of Fabricated TFETs p. 162

6.5 Beyond Low-Power Computation p. 166

6.5.1 Ultrasensitive Biosensor Based on TFET p. 169

6.5.2 Improvement in Biosensor Response Time p. 173

7 Energy-Efficient Computing with Negative Capacitance p. 179 / Asif I. Khan

7.2 How a Negative Capacitance Gate Oxide Leads to Sub-60-Millivolt/Decade Switching p. 181

73 How a Ferroelectric Material Acts as a Negative Capacitor p. 182

7.4 Direct Measurement of Negative Capacitance in Ferroelectric p. 186

7.5 Properties of Negative Capacitance FETs: Modeling and Simulation p. 188

7.6 Experimental Demonstration of Negative Capacitance FETs p. 190

7.7 Speed of Negative Capacitance Transistors p. 195

8 Spin-Based Devices for Logic, Memory, and Non-Boolean Architectures p. 201 / Supriyo Bandyopadhyay

8.2 Spin-Based Devices p. 203

8.2.1 Spin Field-Effect Transistor (SPINFET) p. 205

8.2.2 Single Spin Logic Devices and Circuits p. 209

8.3 Nanomagnetic Devices: A Nanomagnet as a Giant Classical Spin p. 212

8.3.1 Reading Magnetization States (or Stored Bit Information) in Nanomagnets p. 215

8.3.2 Writing Magnetization States (or Storing Bit Information) in Nanomagnets p. 216

8.3.2.1 Spin-Transfer Torque p. 216

8.3.2.2 Spin-Transfer Torque Aided by Giant Spin Hall Effect p. 217

8.3.2.3 Voltage-Controlled Magnetic Anisotropy p. 220

8.3.2.4 Straintronics p. 224

9 Terahertz Properties and Applications of GaN p. 237 / Berardi Sensale-Rodriguez

9.1.1 Applications of Terahertz Technology p. 237

9.1.2 Terahertz Devices and Challenges p. 239

9.2 GaN: Properties and Transport Mechanisms Relevant to THz Applications p. 242

9.2.1 Mobility and Injection Velocity p. 242

9.2.2 Drift Velocity and Negative Differential Resistance p. 245

9.2.3 Transport due to Electron Plasma Waves p. 246

9.3 GaN-based Terahertz Devices: State of the Art p. 249

9.3.1 High-Electron Mobility Transistors p. 249

9.3.2 NDR and Resonant Tunneling Devices p. 252

9.3.3 Quantum Cascade Lasers p. 254

9.3.4 Electron-Plasma-Wave-based Devices p. 254.

Other Format:

ebook version :

ISBN:

9783527343584

352734358X

OCLC:

1079210444