My Account Log in

2 options

Microsystems for bioelectronics : scaling and performance limits / Victor V. Zhirnov, Ralph K. Cavin III ; acquisition editor Simon Holt ; designer Greg Harris.

Ebook Central Academic Complete Available online

View online

O'Reilly Online Learning: Academic/Public Library Edition Available online

View online
Format:
Book
Author/Creator:
Zhirnov, Victor V., author.
Cavin, Ralph K., author.
Contributor:
Holt, Simon, editor.
Harris, Greg, designer.
Series:
Micro & nano technologies.
Micro and Nano Technologies
Language:
English
Subjects (All):
Medical electronics.
Nanomedicine.
Bioelectronics.
Physical Description:
1 online resource (298 p.)
Edition:
Second edition.
Place of Publication:
Amsterdam, [Netherlands] : William Andrew, 2015.
Language Note:
English
System Details:
text file
Summary:
The advances in microsystems offer new opportunities and capabilities to develop systems for biomedical applications, such as diagnostics and therapy. There is a need for a comprehensive treatment of microsystems and in particular for an understanding of performance limits associated with the shrinking scale of microsystems. The new edition of Microsystems for Bioelectronics addresses those needs and represents a major revision, expansion and advancement of the previous edition. This book considers physical principles and trends in extremely scaled autonomous microsystems such as integrated
Contents:
Cover; Title Page; Copyright Page; Contents; Preface-Second Edition; Chapter 1 - The nanomorphic cell: atomic-level limits of computing; List of Acronyms; 1.1 - Introduction; 1.2 - Electronic Scaling; 1.3 - Nanomorphic Cell: Atomic Level Limits of Computing; 1.4 - The Nanomorphic Cell vis-à-vis the Living Cell; 1.5 - Cell Parameters: Mass, Size, and Energy; 1.6 - Current Status of Technologies for Autonomous Microsystems; 1.6.1 - Implantable and Ingestible Medical Devices; 1.6.2 - Intelligent Integrated Sensor Systems; 1.7 - Summary; 1.8 - Appendix; References
Chapter 2 - Basic physics of ICTList of Acronyms; 2.1 - Introduction; 2.2 - A central concept: Energy barrier; 2.3 - Physical origin of the barrier potential in materials systems; 2.4 - Two-sided barrier; 2.4.1 - Example: Electromechanical switch; 2.5 - Model Case: An Electrical Capacitor; 2.6 - Barrier transitions; 2.7 - Quantum Confinement; 2.8 - Quantum conductance; 2.9 - Electron transport in the presence of barriers; 2.9.1 - Over-barrier transport; 2.9.2 - Tunneling transport; 2.10 - Barriers in semiconductors; 2.10.1 - Metal-semiconductor interfaces; 2.10.2 - pn-junction; 2.11 - Summary
ReferencesChapter 3 - Energy in the small: micro-scale energy sources; List of Acronyms; 3.1 - Introduction; 3.2 - Storage Capacitor; 3.2.1 - Example: Maximum energy stored in a capacitor; 3.3 - Electrochemical Energy: Fundamentals of Galvanic Cells; 3.3.1 - Energy Stored in the Galvanic Cell; 3.3.2 - Power Delivery by a Galvanic Cell; 3.3.3 - Current Status of Miniature Galvanic Cells; 3.3.4 - Miniature Biofuel Cells; 3.3.5 - Remarks on Biocompatibility; 3.4 - Miniature Supercapacitors; Miniature supercapacitors: Status and potential directions; 3.5 - Energy from Radioisotopes
3.5.1 - Radioisotope Energy Sources3.5.2 - Radioisotopic Energy Conversion; 3.5.3 - Practical Miniature Radioisotope Energy Sources; 3.6 - Remarks on Energy Harvesting; 3.6.1 - Photovoltaics; 3.6.2 - Radio Frequency (RF)/Microwave Energy Harvesting; 3.6.3 - Kinetic Energy Harvesting; 3.6.4 - Thermal Energy Harvesting; 3.7 - Summary; 3.8 - Appendix. A kinetic model to assess the limits of heat removal; References; Chapter 4 - Fundamental limits for logic and memory; List of Acronyms; 4.1 - Introduction; 4.2 - Information and Information Processing; 4.3 - Basic Physics of Binary Elements
4.3.1 - Distinguishable States4.3.2 - Energy Barrier Framework for the Operating Limits of Binary Switches; A. Limits on barrier height; B. Limits on Size; C. Limits on Speed; D. Combined Effect of Classic and Quantum Errors; 4.3.3 - A summary of device scaling limits; 4.3.4 - Charge-based Binary Logic Switch; 4.3.5 - Charge-based Memory Element; DRAM; SRAM; Floating gate/flash memory; 4.4 - System-level Analysis; 4.4.1 - Tiling Considerations: Device density; 3D Tiling of Flash Memory; 4.4.2 - Energy adjustment for system reliability; 4.4.3 - Models for Connected Binary Switches
A. Juxtaposed Switches
Notes:
Description based upon print version of record.
Includes bibliographical references at the end of each chapters and index.
Description based on online resource; title from PDF title page (ebrary, viewed March 14, 2015).
ISBN:
9780323312691
0323312691
OCLC:
905984644

The Penn Libraries is committed to describing library materials using current, accurate, and responsible language. If you discover outdated or inaccurate language, please fill out this feedback form to report it and suggest alternative language.

My Account

Shelf Request an item Bookmarks Fines and fees Settings

Guides

Using the Library Catalog Using Articles+ Library Account