Finite state machines in hardware : theory and design (with VHDL and SystemVerilog) / Volnei A. Pedroni.

Format:

Book

Author/Creator:

Pedroni, Volnei A., author.

Language:

English

Subjects (All):

Computer systems--Mathematical models.

Computer systems.

Sequential machine theory--Data processing.

Sequential machine theory.

SystemVerilog (Computer hardware description language).

VHDL (Computer hardware description language).

Mathematical models.

Physical Description:

1 online resource (x, 337 pages) : illustrations

Other Title:

MIT Press CogNet.

Place of Publication:

Cambridge, Massachusetts : The MIT Press, [2014]

System Details:

text file

Summary:

Modern, complex digital systems invariably include hardware-implemented finite state machines. The correct design of such parts is crucial for attaining proper system performance. This book offers detailed, comprehensive coverage of the theory and design for any category of hardware-implemented finite state machines. It describes crucial design problems that lead to incorrect or far from optimal implementation and provides examples of finite state machines developed in both VHDL and SystemVerilog (the successor of Verilog) hardware description languages. Important features include: extensive review of design practices for sequential digital circuits; a new division of all state machines into three hardware-based categories, encompassing all possible situations, with numerous practical examples provided in all three categories; the presentation of complete designs, with detailed VHDL and SystemVerilog codes, comments, and simulation results, all tested in FPGA devices; and exercise examples, all of which can be synthesized, simulated, and physically implemented in FPGA boards. Additional material is available on the book's Website. Designing a state machine in hardware is more complex than designing it in software. Although interest in hardware for finite state machines has grown dramatically in recent years, there is no comprehensive treatment of the subject. This book offers the most detailed coverage of finite state machines available. It will be essential for industrial designers of digital systems and for students of electrical engineering and computer science. Book jacket.

Contents:

1 The Finite State Machine Approach 1

1.1 Introduction 1

1.2 Sequential Circuits and State Machines 1

1.3 State Transition Diagrams 4

1.4 Equivalent State Transition Diagram Representations 6

1.5 Under- and Overspecified State Transition Diagrams 8

1.6 Transition Types 11

1.7 Moore-to-Mealy Conversion 12

1.8 Mealy-to-Moore Conversion 14

1.9 Algorithmic State Machine Chart 15

1.10 When to Use the FSM Approach 16

1.11 List of Main Machines Included in the Book 17

1.12 Exercises 18

2 Hardware Fundamentals-Part I 21

2.1 Introduction 21

2.2 Flip-Flops 21

2.3 Metastability and Synchronizers 24

2.4 Pulse Detection 28

2.5 Glitches 29

2.6 Pipelined Implementations 32

2.7 Exercises 33

3 Hardware Fundamentals-Part II 39

3.1 Introduction 39

3.2 Hardware Architectures for State Machines 39

3.3 Fundamental Design Technique for Moore Machines 41

3.4 Fundamental Design Technique for Mealy Machines 44

3.5 Moore versus Mealy Time Behavior 46

3.6 State Machine Categories 47

3.7 State-Encoding Options 49

3.7.1 Sequential Binary Encoding 49

3.7.2 One-Hot Encoding 50

3.7.3 Johnson Encoding 50

3.7.4 Gray Encoding 50

3.7.5 Modified One-Hot Encoding with All-Zero State 51

3.7.6 Other Encoding Schemes 52

3.8 The Need for Reset 52

3.9 Safe State Machines 54

3.10 Capturing the First Bit 56

3.11 Storing the Final Result 58

3.12 Multimachine Designs 60

3.13 State Machines for Datapath Control 62

3.14 Exercises 67

4 Design Steps and Classical Mistakes 73

4.1 Introduction 73

4.2 Classical Problems and Mistakes 73

4.2.1 Skipping the State Transition Diagram 73

4.2.2 Wrong Architecture 73

4.2.3 Incorrect State Transition Diagram Composition 74

4.2.4 Existence of State Bypass 75

4.2.5 Lack of Reset 75

4.2.6 Lack of Synchronizers 76

4.2.7 Incorrect Timer Construction 76

4.2.8 Incomplete VHDL/SystemVerilog Code 76

4.2.9 Overregistered VHDL/SystemVerilog Code 78

4.3 Design Steps Summary 79

5 Regular (Category 1) State Machines 81

5.1 Introduction 81

5.2 Architectures for Regular (Category 1) Machines 82

5.3 Number of Flip-Flops 84

5.4 Examples of Regular (Category 1) Machines 84

5.4.1 Small Counters 84

5.4.2 Parity Detector 85

5.4.3 Basic One-Shot. Circuit 86

5.4.4 Temperature Controller 88

5.4.5 Garage Door Controller 89

5.4.6 Vending Machine Controller 90

5.4.7 Datapath Control for an Accumulator 91

5.4.8 Datapath Control for a Greatest Common Divisor Calculator 93

5.4.9 Generic Sequence Detector 95

5.4.10 Transparent Circuits 96

5.4.11 LCD, l²C, and SPI Interfaces 97

5.5 Exercises 97

6 VHDL Design of Regular (Category 1) State Machines 105

6.1 Introduction 105

6.2 General Structure of VHDL Code 105

6.3 VHDL Template for Regular (Category 1) Moore Machines 107

6.4 Template Variations 111

6.4.1 Combinational Logic Separated into Two Processes 111

6.4.2 State Register Plus Output Register in a Single Process 112

6.4.3 Using Default Values 112

6.4.4 A Dangerous Template 113

6.5 VHDL Template for Regular (Category 1) Mealy Machines 114

6.6 Design of a Small Counter 116

6.7 Design of a Garage Door Controller 120

6.8 Design of a Datapath Controller for a Greatest Common Divisor Calculator 123

6.9 Exercises 126

7 SystemVerilog Design of Regular (Category 1) State Machines 129

7.1 Introduction 129

7.2 General Structure of SystemVerilog Code 129

7.3 SystemVerilog Template for Regular (Category 1) Moore Machines 130

7.4 SystemVerilog Template for Regular (Category 1) Mealy Machines 133

7.5 Design of a Small Counter 135

7.6 Design of a Garage Door Controller 137

7.7 Design of a Datapath Controller for a Greatest Common Divisor Calculator 140

7.8 Exercises 141

8 Timed (Category 2) State Machines 143

8.1 Introduction 143

8.2 Architectures for Timed (Category 2) Machines 144

8.3 Timer Interpretation 146

8.3.1 Time Measurement Unit 146

8.3.2 Timer Range 146

8.3.3 Number of Bits 146

8.4 Transition Types and Timer Usage 147

8.5 Timer Control Strategies 147

8.5.1 Preliminary Analysis 148

8.5.2 Timer Control Strategy #1 (Generic) 149

8.5.3 Timer Control Strategy #2 (Nongeneric) 150

8.5.4 Time Behavior of Strategies #1 and #2 151

8.6 Truly Complementary Time-Based Transition Conditions 153

8.7 Repetitively Looped State Machines 154

8.8 Time Behavior of Timed Moore Machines 155

8.9 Time Behavior of Timed Mealy Machines 156

8.10 Number of Flip-Flops 158

8.11 Examples of Timed (Category 2) Machines 158

8.11.1 Blinking Light 159

8.11.2 Light Rotator 160

8.11.3 Switch Debouncer 161

8.11.4 Reference-Value Definer 163

8.11.5 Traffic Light Controller 166

8.11.6 Car Alarm (with Chirps) 167

8.11.7 Password Detector 168

8.11.8 Triggered Circuits 170

8.11.9 Pulse Shifter 172

8.11.10 Pulse Stretchers 173

8.12 Exercises 176

9 VHDL Design of Timed (Category 2) State Machines 185

9.1 Introduction 185

9.2 VHDL Template for Timed (Category 2) Moore Machines 185

9.3 VHDL Template for Timed (Category 2) Mealy Machines 189

9.4 Design of a Light Rotator 191

9.5 Design of a Car Alarm (with Chirps) 194

9.6 Design of a Triggered Monostable Circuit 198

9.7 Exercises 201

10 SystemVerilog Design of Timed (Category 2) State Machines 207

10.1 Introduction 207

10.2 SystemVerilog Template for Timed (Category 2) Moore Machines 207

10.3 SystemVerilog Template for Timed (Category 2) Mealy Machines 210

10.4 Design of a Light Rotator 212

10.5 Design of a Car Alarm (with Chirps) 214

10.6 Design of a Triggered Monostable Circuit 217

10.7 Exercises 220

11 Recursive (Category 3) State Machines 221

11.1 Introduction 221

11.2 Recursive (Category 3) State Machines 222

11.3 Architectures for Recursive (Category 3) Machines 223

11.4 Category 3 to Category 1 Conversion 224

11.5 Repetitively Looped Category 3 Machines 225

11.6 Number of Flip-Flops 226

11.7 Examples of Recursive (Category 3) State Machines 226

11.7.1 Generic Counters 226

11.7.2 Long-String Comparator 228

11.7.3 Reference-Value Definer 229

11.7.4 Reference-Value Definer with Embedded Debouncer 231

11.7.5 Datapath Control for a Sequential Multiplier 232

11.7.6 Sequential Divider 234

11.7.7 Serial Data Receiver 236

11.7.8 Memory Interface 237

11.8 Exercises 240

12 VHDL Design of Recursive (Category 3) State Machines 245

12.1 Introduction 245

12.2 VHDL Template for Recursive (Category 3) Moore Machines 245

12.3 VHDL Template for Recursive (Category 3) Mealy Machines 248

12.4 Design of a Datapath Controller for a Multiplier 249

12.5 Design of a Serial Data Receiver 252

12.6 Design of a Memory Interface 256

12.7 Exercises 261

13 SystemVerilog Design of Recursive (Category 3) State Machines 265

13.1 Introduction 265

13.2 SystemVerilog Template for Recursive (Category 3) Moore Machines 265

13.3 SystemVerilog Template for Recursive (Category 3) Mealy Machines 267

13.4 Design of a Datapath Controller for a Multiplier 268

13.5 Design of a Serial Data Receiver 271

13.6 Design of a Memory Interface 273

13.7 Exercises 278

14 Additional Design Examples 279

14.1 LCD Driver 279

14.1.1 Alphanumeric LCD 279

14.1.2 Typical FSM Structure for Alphanumeric LCD Drivers 283

14.1.3 Complete Design Example: Clock with LCD Display 284

14.2 I²C Interface 290

14.2.1 I²C Bus Structure 290

14.2.2 Open-Drain Outputs 291

14.2.3 I²C Bus Operation 292

14.2.4 Typical FSM Structure for I²C Applications 295

14.2.5 Complete Design Example: RTC (Real-Time Clock) Interface 296

14.3 SPI Interface 305

14.3.1 SPI Bus Structure 305

14.3.2 SPI Bus Operation 306

14.3.3 Complete Design Example: FRAM (Ferroelectric RAM) Interface 307

14.4 Exercises 315

15 Pointer-Based FSM Implementation 319

15.1 Introduction 319

15.2 Single-Loop FSM 319

15.3 Serial Data Transmitter 321

15.4 Serial Data Receiver 322

15.5 SPI Interface for an FRAM 325

15.6 Exercises 329.

Notes:

Includes bibliographical references.

Description based on print version record.

Other Format:

Print version: Pedroni, Volnei A. Finite state machines in hardware.

ISBN:

9780262319096

0262319098

Access Restriction:

Restricted for use by site license.