2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) : 7-10 Oct. 2013, Monterey, California, USA / Institute of Electrical and Electronics Engineers.

Format:

Book

Author/Creator:

Institute of Electrical and Electronics Engineers, author, issuing body.

Language:

English

Subjects (All):

Microelectronics--Congresses.

Microelectronics.

Semiconductors--Congresses.

Semiconductors.

Physical Description:

1 online resource (212 pages) : illustrations

Other Title:

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference

SOI-3D-Subthreshold Microelectronics Technology Unified Conference

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S 2013)

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S 2013)/frim

Place of Publication:

Monterey, California : IEEE, 2013.

Contents:

Conference committee

List of presentations

General chairman's welcome

Author index

Introduction and history [of the IEEE S3S Conference]

[Title page]

Fully-depleted-silicon-on-insulator from R&D concept to industrial reality

Practical process flows for monolithic 3D

3D integration of high mobility InGaAs nFETs and Ge pFETs for ultra low power and high performance CMOS

3D-enabled heterogeneous integrated circuits

Three-dimensional wafer stacking using Cu TSV integrated with 45nm high performance SOI-CMOS embedded DRAM technology

3D hetero-integration technology with backside TSV and reliability challenges

Fine grained 3D cache architecture using high density TSVs

SOI lateral bipolar transistor with drive current >3mA/µm

Three-dimensional integrated circuits with NFET and PFET on separate layers fabricated by low temperature Au/SiO2 hybrid bonding

Aggressively scaled strained silicon directly on insulator (SSDOI) FinFETs.

Notes:

Description based on publisher supplied metadata and other sources.

ISBN:

9781479913619

1479913618