2014 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) / Institute of Electrical and Electronics Engineers.

Format:

Book

Author/Creator:

Institute of Electrical and Electronics Engineers, author, issuing body.

Language:

English

Subjects (All):

Microelectronics--Congresses.

Microelectronics.

Physical Description:

1 online resource

Other Title:

2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference

SOI-3D-Subthreshold Microelectronics Technology Unified Conference

Place of Publication:

Piscataway : IEEE, 2014.

Summary:

This new unified conference will help us to improve our efficiency and establish this conference as a world class International venue to present and learn about the most up to date trends in CMOS and post CMOS Scaling The conference committee hopes you will enjoy this new conference that will give you more opportunities to learn and gain insight into the different contributions to the low power SOC eco system.

Contents:

The role of the cloud in Machine to Machine & Internet of Things computing best practices, key insights and guidance to connecting devices to the cloud,"B.

Advanced High K/Metal SOI technologies for 32nm and beyond,"M.

A 361nA thermal run-away immune VBB generator using dynamic substrate controlled charge pump for ultra low sleep current logic on 65nm SOTB,"H.

A 53µW âˆ'82dBm sensitivity 920MHz OOK receiver design using bias switch technique on 65nm SOTB CMOS technology,"H.

SOI FinFET versus bulk FinFET for 10nm and below,"T.

High mobility w-gate nanowire P-FET on cSGOI substrates obtained by Ge enrichment technique,"P.

Dielectric isolated FinFETs on bulk substrate,"D.

Elastic relaxation in intrinsically-strained Fins: Simulations, physical and electrical characterization,"F.

Toward robust subthreshold circuit design - Variability and soft error perspective,"M.

Energy efficiency benefits of subthreshold-optimized transistors for digital logic,"P.

Ultra-wide voltage range 32-bit RISC CPU with timing-error prevention in 28nm CMOS,"M.

A reduced-memory FIR filter using approximate coefficients for ultra-low power SoCs,"A.

Monolithic 3D integration: A powerful alternative to classical 2D scaling,"M.

Design challenges and solutions for ultra-high-density monolithic 3D ICs,"S.

3D memory with shared lithography steps: The memory industry's plan to “cram more components onto integrated circuitsâ€,"D.

Monolithic 3D integration in a CMOS process flow,"E.

Monolithic 3D integration advances and challenges: From technology to system levels,"M.

Performance assessment of ULP analog/RF MOSFET architectures,"D.

Effects of back-gate bias on switched-capacitor DC-DC converters in UTBB FD-SOI,"M.

An optimal probing method of pre-bond TSV fault identification in 3D stacked ICs,"B.

Power supply voltage detection and clamping circuit for 3-D integrated circuits,"D.

Study of fin-tunnel FETs with doped pocket as capacitor-less 1T DRAM,"A.

On the cryogenic performance of ultra-low-loss, wideband SPDT RF switches designed in a 180 nm SOI-CMOS technology,"A.

Analog performance of short-channel asymmetric self-cascode of junctionless nanowire nMOS transistors,"M.

Multi-threshold design methodology of stacked Si-nanowire FETs,"Y.

Analog building block design in 14nm FinFET using inversion coefficient,"A.

28 nm FD SOI Technology Platform RF FoM,"B.

An SOI based integrated gate-drivers for automotive application,"K.

Effect of back gate on parasitic bipolar effect in FD SOI MOSFETs,"F.

High temperature performance of flexible SOI FinFETs with sub-20 nm fins,"A.

UTBB/FDSOI: Reasons for a success,"M.

Piezoresistivity in unstrained and strained SOI MOSFETs,"R.

nFET FDSOI activated by low temperature solid phase epitaxial regrowth: Optimization guidelines,"L.

In depth characterization of hole transport in 14nm FD-SOI pMOS devices,"M.

Influence of underlap on UTBB SOI MOSFETs in dynamic threshold mode,"K.

Near-0.1V ultra-low voltage operation of SOTB 1M logic gates,"Y.

Performance prediction for multiple-threshold 7nm-FinFET-based circuits operating in multiple voltage regimes using a cross-layer simulation framework,"S.

A cross-layer design framework and comparative analysis of SRAM cells and cache memories using 7nm FinFET devices,"A.

Efficient ultra low power rectification at 13.56 MHz for a 10 µA load current,"P.

Experimental model of adaptive body biasing for energy efficiency in 28nm UTBB FD-SOI,"M.

UTBB FD-SOI front- and back-gate coupling aware random telegraph signal impact analysis on a 6T SRAM,"K.

Mixed-single well 8T SRAM bitcell for wide voltage range in 28nm FDSOI,"A.

A tunnel-FET SRAM array for energy-efficient embedded memory blocks in reconfigurable computing platforms,"M.

Impacts of work function variation and line-edge roughness on TFET and FinFET devices and logic circuits,"C.

OxRAM-based pulsed latch for non-volatile flip-flop in 28nm FDSOI,"A.

Electron-hole bilayer deep subthermal electronic switch: Physics, promise and challenges,"

Beyond TFET: Alternative mechanisms for CMOS-compatible sharp-switching devices,"

A2RAM: Low-power 1T-DRAM memory cells compatible with planar and 3D SOI substrates,"

Bias-flip technique for frequency tuning of piezo-electric energy harvesting devices: Experimental verification,"

Adaptive subthreshold switched capacitor voltage boost for thermoelectric generation,"

SOI substrate solutions for recent advanced device applications,"

The role of radiation effects in SOI technology development,"

A very low power CMOS 28FDSOI programmable fractional frequency divider for Wifi-WiGig,"

Recent advances and future trends in SOI for RF applications,"

SEU Hardening: Incorporating an Extreme Low Power Bitcell Design (SHIELD),"

Impact of ultra-low voltages on single-event transients and pulse quenching,"

Compensation of total ionizing dose effects in ULV SoCs through adaptive voltage scaling,"

Near-threshold voltage operation of a nonvolatile SRAM cell based on pseudo-spin-FinFET architecture,"

More than an order of magnitude energy improvement of FPGA by combining 0.4V operation and Multi-Vt optimization of 20k body bias domains,"H.

Monolithic IC integration key alignment aspects for high process yield,"

New precision alignment methodology for CMOS wafer bonding,"

Precision bonders - A game changer for monolithic 3D,"

Fully functional fine-grain vertically integrated 3D focal plane neuromorphic processor,"

Smart co-integration of light sensitive layers with FDSOI transistors for More than Moore applications,"

Prototype of multi-stacked memory wafers using low-temperature oxide bonding and ultra-fine-dimension copper through-silicon via interconnects,"W.

A 262nW analog front end with a digitally-assisted low noise amplifier for batteryless EEG acquisition,".

Notes:

Description based on publisher supplied metadata and other sources.

ISBN:

1-4799-7439-0