Millimeter-wave digitally intensive frequency generation in CMOS / Wanghua Wu, Robert Bogdan Staszewski, John R. Long.

Format:

Book

Author/Creator:

Wu, Wanghua, author.

Staszewski, Robert Bogdan, author.

Long, John R., author.

Language:

English

Subjects (All):

Frequency synthesizers.

Metal oxide semiconductors, Complementary.

Physical Description:

1 online resource (0 p.)

Edition:

1st ed.

Place of Publication:

Amsterdam, [Netherlands] : Academic Press, 2016.

Language Note:

English

Summary:

This book describes the digitally intensive time-domain architectures and techniques applied to millimeter-wave frequency synthesis, with the objective of improving performance and reducing the cost of implementation.

Contents:

Front Cover

Millimeter-Wave Digitally Intensive Frequency Generation in CMOS

Copyright Page

Contents

Preface

List of Abbreviations

1 Introduction

1.1 Motivation

1.1.1 Advantages of Millimeter-Wave Radios

1.1.2 Deep-Submicron CMOS

1.1.3 Digitally Intensive Approach

1.2 Design Challenges

1.2.1 Toward All-Digital PLL in mm-Wave Regime

1.2.2 Wide Tuning Range and Fine Frequency Resolution

1.2.3 Linear Wideband FM

References

2 Millimeter-Wave Frequency Synthesizers

2.1 Frequency Synthesizer Fundamentals

2.1.1 PN in Oscillators

2.1.2 Frequency Synthesizer in a Radio Transceiver

2.1.3 Methods for Frequency Synthesis

2.2 Phase-Locked Loop

2.2.1 Charge-Pump PLL

2.2.2 All-Digital PLL

2.3 Millimeter-Wave PLL Architectures

2.3.1 PLL with a Fundamental Oscillator

2.3.2 PLL-Based Harmonic Generation

2.4 Summary

3 Circuit Design Techniques for mm-Wave Frequency Synthesizer

3.1 Wideband Oscillator

3.1.1 Oscillator with Switched-Capacitor Tuning

3.1.2 Oscillator with Switched-Inductor Tuning

3.1.3 Transformer-Coupled Oscillator

3.2 High-Frequency Divider

3.2.1 Regenerative Frequency Divider

3.2.2 CML Divider

3.2.3 Digital CMOS Divider

3.3 Frequency Multiplier

3.4 Summary

4 All-Digital Phase-Locked Loop

4.1 Phase-Domain Operation

4.2 Reference Clock Retiming

4.3 DCO Gain Normalization and Estimation

4.4 Loop Gain Factor and Gear Shifting of the PLL Gain

4.4.1 Loop Gain Factor

4.4.2 Gear Shifting PLL Gain

4.5 PLL Frequency Response

4.6 Noise and Error Sources

4.7 Behavioral Modeling and Simulation Approach

4.8 Summary

5 Millimeter-Wave Digitally Controlled Oscillator

5.1 From Low-Gigahertz DCOs to mm-Wave DCOs.

5.2 Reconfigurable Resonator with Distributed Metal Capacitors

5.3 Fine-Tuning Techniques to Achieve High-Frequency Resolution

5.3.1 Inductor with Distributed Switched-C for Fine-Tuning

5.3.2 Transformer-Coupled Fine-Tuning Bank

5.4 Example Implementation of 60-GHz DCOs

5.4.1 L-DCO

5.4.2 T-DCO

5.4.3 Experiment Results

5.4.3.1 Differential TL Test Structure

5.4.3.2 L-DCO Measurement Results

5.4.3.3 T-DCO Measurement Results

5.5 Summary

6 Application: A 60-GHz All-Digital PLL for FMCW Transmitter Applications

6.1 Design Specification

6.1.1 Frequency Modulation Range (BW)

6.1.2 Frequency Modulation Period (Tmod)

6.1.3 Phase Noise

6.1.4 Frequency Sweep Linearity and Quantization Effect

6.2 Multi-Rate ADPLL-Based Frequency Modulator

6.2.1 60-GHz ADPLL

6.2.2 Wideband Frequency Modulation

6.3 DCO Interfacing

6.3.1 Separate DCO Fine-Tuning Bank for CW and FM

6.3.2 Decoder Mapping Algorithm for Device Matching

6.4 Divider Chain Design

6.4.1 Circuit Design

6.4.2 Simulated Performance

6.5 TDC Design and Calibration

6.5.1 TDC Core Architecture

6.5.2 TDC Unit Cell Design

6.5.3 TDC Calibration

6.5.4 Simulated Performance

6.6 Reference Slicer Design

6.6.1 Circuit Design

6.6.2 Simulated Performance

6.7 Phase Error Generation and Glitch Removal

6.8 Top-Level Floor Plan Considerations for mm-Wave ADPLL

6.9 Experiment Results for 60-GHz ADPLL

6.10 Summary

7 Digital Techniques for Higher RF Performance

7.1 Frequency Tuning Nonlinearity in a Multibank DCO

7.2 Multibank DCO Gain Calibration and Linearization

7.3 Mismatch Calibration of the Fine-Tuning Bank

7.4 Synchronization in a Multirate System

7.5 Experimental Results of FMCW Transmitter

7.5.1 FSK Modulation

7.5.2 FMCW Modulation

7.6 Summary.

References

8 Design for Test of the mm-Wave ADPLL

8.1 Testing Challenges for the RF Synthesizer

8.2 Critical Signals in ADPLL for DFT and DFC

8.3 DFT Techniques for ADPLL

8.3.1 Snapshotting Internal Signals for DFT and DFC

8.3.2 Performance-Based BIST and BISC

8.3.2.1 DCO Tuning Step Analyzer

8.3.2.2 Built-in Phase Error (ΦE) Analyzer

8.4 Measurement Setup and Procedures

8.4.1 Measurement Setup

8.4.2 Test Procedures and Test Modes

8.5 Summary

Index

Back Cover.

Notes:

Description based upon print version of record.

Includes bibliographical references at the end of each chapters and index.

Description based on online resource; title from PDF title page (ebrary, viewed November 27, 2015).

Description based on publisher supplied metadata and other sources.

ISBN:

9780128023617

0128023619

9780128022078

0128022078

OCLC:

932328800