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Stress management for 3D ICs using through silicon vias : International Workshop on Stress Management for 3D ICs Using Through Silicon Vias, Albany, NY, U.S.A, March 16, 2010, San Francisco, CA, U.S.A., July 13, 2010, Dresden, Germany, October 20, 2010
- Format:
- Book
- Conference/Event
- Author/Creator:
- International Workshop on Stress Management for 3D ICs Using Through Silicon Vias, Corporate Author.
- Conference Name:
- International Workshop on Stress Management for 3D ICs Using Through Silicon Vias (2010 : Albany, N.Y.)
- International Workshop on Stress Management for 3D ICs Using Through Silicon Vias
- Series:
- AIP conference proceedings Stress management for 3D ICs using through silicon vias
- Language:
- English
- Subjects (All):
- Three-dimensional integrated circuits--Design and construction--Congresses.
- Three-dimensional integrated circuits.
- Stress relaxation (Physics)--Simulation methods--Congresses.
- Stress relaxation (Physics).
- Strains and stresses--Simulation methods--Congresses.
- Strains and stresses.
- Strains and stresses--Measurement--Congresses.
- Other Title:
- Stress Management For 3D Ics Using Through Silicon Vias: International Workshop On Stress Management For 3D Ics Using Through Silicon Vias, Volume 1378
- Stress Management For 3D Ics Using Through Silicon Vias
- Place of Publication:
- [Place of publication not identified] American Institute of Physics 2011
- Language Note:
- English
- Contents:
- White papers
- Multi-scale modeling
- Multi-scale materials parameters
- Multi-scale stress characterization
- TSV : process characterization and failure analysis.
- Notes:
- Bibliographic Level Mode of Issuance: Monograph
- ISBN:
- 0-7354-0938-2
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