Design recipes for FPGAs / Peter R. Wilson.

Format:

Book

Author/Creator:

Wilson, Peter R. (Peter Robert), 1939-

Language:

English

Subjects (All):

Field programmable gate arrays--Design and construction.

Field programmable gate arrays.

Gate array circuits.

Physical Description:

xxii, 289 p. : ill.

Edition:

1st ed.

Place of Publication:

Amsterdam ; Boston ; London : Newnes, 2007.

Summary:

A rich treasure chest of design techniques and templates for solving practical, every-day problems using FPGAs.

Contents:

Front cover

Design Recipes for FPGAs

Copyright page

Contents

Acknowledgements

Preface

List of Figures

Part 1 Overview

Chapter 1 Introduction

Why FPGAs?

Chapter 2 An FPGA Primer

Introduction

FPGA evolution

Programmable logic devices

Field programmable gate arrays

FPGA design techniques

Design constraints using FPGAs

Summary

Chapter 3 A VHDL Primer The Essentials

Entity: model interface

Architecture: model behavior

Process: basic functional unit in VHDL

Basic variable types and operators

Decisions and loops

Hierarchical design

Debugging models

Basic data types

Chapter 4 Design Automation and Testing for FPGAs

Simulation

Libraries

Synthesis

Physical design flow

Place and route

Timing analysis

Design pitfalls

VHDL issues for FPGA design

Part 2 Applications

Chapter 5 Images and High-Speed Processing

The camera link interface

Getting started

Specifying the interfaces

Defining the top level design

System block definitions and interfaces

The cameralink interface

The PC interface

Chapter 6 Embedded Processors

A simple embedded processor

Soft core processors on an FPGA

Part 3 Designer's Toolbox

Chapter 7 Serial Communications

Manchester encoding and decoding

NRZ coding and decoding

NRZI coding and decoding

RS-232

Universal Serial Bus

Chapter 8 Digital Filters

Converting S-domain to Z-domain

Implementing Z-domain functions in VHDL

Basic low pass filter model

FIR filters

IIR filters

Chapter 9 Secure Systems

Introduction to block ciphers

Feistel lattice structures

The Data Encryption Standard

Advanced Encryption Standard.

Implementing AES in VHDL

Chapter 10 Memory

Modeling memory in VHDL

Read Only Memory

Random Access Memory

Synchronous RAM

FLASH memory

Chapter 11 PS/2 Mouse Interface

PS/2 mouse basics

PS/2 mouse commands

PS/2 mouse data packets

PS/2 operation modes

PS/2 mouse with wheel

Basic PS/2 mouse handler VHDL

Modified PS/2 mouse handler VHDL

Chapter 12 PS/2 Keyboard Interface

PS/2 keyboard basics

PS/2 keyboard commands

PS/2 keyboard data packets

PS/2 keyboard operation modes

Chapter 13 A Simple VGA Interface

Basic pixel timing

Image handling

VGA interface VHDL

Horizontal sync

Vertical sync

Horizontal and vertical blanking pulses

Calculating the correct pixel data

Part 4 Optimizing Designs

Chapter 14 Synthesis

VHDL supported in RTL synthesis

Some interesting cases where synthesis may fail

What is being synthesized?

Chapter 15 Behavioral Modeling in VHDL

How to go from RTL to behavioral VHDL

Chapter 16 Design Optimization

Techniques for logic optimization

Improving performance

Critical path analysis

Chapter 17 VHDL-AMS

Introduction to VHDL-AMS

Analog pins: TERMINALS

Mixed-domain modeling

Analog variables: quantities

Simultaneous equations in VHDL-AMS

A VHDL-AMS example

Differential equations in VHDL-AMS

Mixed-signal modeling with VHDL-AMS

A basic switch model

Basic VHDL-AMS comparator model

Multiple domain modeling

Chapter 18 Design Optimization Example: DES

The DES

Moods

Initial design

Initial synthesis

Optimizing the data path

Final optimization.

Results

Triple DES

Comparing the approaches

Part 5 Fundamental Techniques

Chapter 19 Counters

Basic binary counter

Synthesized simple binary counter

Shift register

The Johnson counter

BCD counter

Chapter 20 Latches, Flip-Flops and Registers

Latches

Flip-flops

Registers

Chapter 21 Serial to Parallel &amp

Parallel to Serial Conversion

Serial to Parallel Conversion

Chapter 22 ALU Functions

Logic functions

1-bit adder

Structural n-bit addition

Configurable n-bit addition

Twos complement

Chapter 23 Decoders and Multiplexers

Decoders

Multiplexers

Chapter 24 Finite State Machines in VHDL

State transition diagrams

Implementing FSM in VHDL

Chapter 25 Fixed Point Arithmetic in VHDL

Basic fixed point types

Fixed point functions

Testing the fixed point function

Chapter 26 Binary Multiplication

Basic binary multiplication

VHDL unsigned multiplier

Synthesis of the multiplication function

'Simple' multiplication

Chapter 27 Bibliography

Useful texts for VHDL

Useful Texts for FPGAs

General Digital Design Books

Index

A

B

C

D

E

F

L

M

P

R

S

V

Z.

Notes:

Includes bibliographical references (p. [284]-285) and index.

OCLC:

476083031