Digital design and computer architecture / David Money Harris, Sarah L. Harris.

Format:

Book

Author/Creator:

Harris, David Money.

Contributor:

Harris, Sarah L.

Language:

English

Subjects (All):

Digital electronics.

Logic design.

Computer architecture.

Physical Description:

1 online resource (593 p.)

Edition:

1st ed.

Place of Publication:

Amsterdam ; Boston : Morgan Kaufmann Publishers, c2007.

Language Note:

English

System Details:

text file

Summary:

Digital Design and Computer Architecture is designed for courses that combine digital logic design with computer organization/architecture or that teach these subjects as a two-course sequence. Digital Design and Computer Architecture begins with a modern approach by rigorously covering the fundamentals of digital logic design and then introducing Hardware Description Languages (HDLs). Featuring examples of the two most widely-used HDLs, VHDL and Verilog, the first half of the text prepares the reader for what follows in the second: the design of a MIPS Processor. By the end of D

Contents:

Front cover; In Praise of Digital Design and Computer Architecture; About the Authors; Title page; Copyright page; Table of contents; Preface; FEATURES; ONLINE SUPPLEMENTS; HOW TO USE THE SOFTWARE TOOLS IN A COURSE; Xilinx ISE WebPACK; Synplify Pro; PCSPIM; LABS; BUGS; ACKNOWLEDGMENTS; Chapter 1 From Zero to One; 1.1 THE GAME PLAN; 1.2 THE ART OF MANAGING COMPLEXITY; 1.2.1 Abstraction; 1.2.2 Discipline; 1.2.3 The Three -Y's; 1.3 THE DIGITAL ABSTRACTION; 1.4 NUMBER SYSTEMS; 1.4.1 Decimal Numbers; 1.4.2 Binary Numbers; 1.4.3 Hexadecimal Numbers; 1.4.4 Bytes, Nibbles, and All That Jazz

1.4.5 Binary Addition1.4.6 Signed Binary Numbers; 1.5 LOGIC GATES; 1.5.1 NOT Gate; 1.5.2 Buffer; 1.5.3 AND Gate; 1.5.4 OR Gate; 1.5.5 Other Two-Input Gates; 1.5.6 Multiple-Input Gates; 1.6 BENEATH THE DIGITAL ABSTRACTION; 1.6.1 Supply Voltage; 1.6.2 Logic Levels; 1.6.3 Noise Margins; 1.6.4 DC Transfer Characteristics; 1.6.5 The Static Discipline; 1.7 CMOS TRANSISTORS; 1.7.1 Semiconductors; 1.7.2 Diodes; 1.7.3 Capacitors; 1.7.4 nMOS and pMOS Transistors; 1.7.5 CMOS NOT Gate; 1.7.6 Other CMOS Logic Gates; 1.7.7 Transmission Gates; 1.7.8 Pseudo-nMOS Logic; 1.8 POWER CONSUMPTION

1.9 SUMMARY AND A LOOK AHEADExercises; Interview Questions; Chapter 2 Combinational Logic Design; 2.1 INTRODUCTION; 2.2 BOOLEAN EQUATIONS; 2.2.1 Terminology; 2.2.2 Sum-of-Products Form; 2.2.3 Product-of-Sums Form; 2.3 BOOLEAN ALGEBRA; 2.3.1 Axioms; 2.3.2 Theorems of One Variable; 2.3.3 Theorems of Several Variables; 2.3.4 The Truth Behind It All; 2.3.5 Simplifying Equations; 2.4 FROM LOGIC TO GATES; 2.5 MULTILEVEL COMBINATIONAL LOGIC; 2.5.1 Hardware Reduction; 2.5.2 Bubble Pushing; 2.6 X'S AND Z'S, OH MY; 2.6.1 Illegal Value: X; 2.6.2 Floating Value: Z; 2.7 KARNAUGH MAPS

2.7.1 Circular Thinking2.7.2 Logic Minimization with K-Maps; 2.7.3 Don't Cares; 2.7.4 The Big Picture; 2.8 COMBINATIONAL BUILDING BLOCKS; 2.8.1 Multiplexers; 2.8.2 Decoders; 2.9 TIMING; 2.9.1 Propagation and Contamination Delay; 2.9.2 Glitches; 2.10 SUMMARY; Exercises; Interview Questions; Chapter 3 Sequential Logic Design; 3.1 INTRODUCTION; 3.2 LATCHES AND FLIP-FLOPS; 3.2.1 SR Latch; 3.2.2 D Latch; 3.2.3 D Flip-Flop; 3.2.4 Register; 3.2.5 Enabled Flip-Flop; 3.2.6 Resettable Flip-Flop; 3.2.7 Transistor-Level Latch and Flip-Flop Designs; 3.2.8 Putting It All Together

3.3 SYNCHRONOUS LOGIC DESIGN3.3.1 Some Problematic Circuits; 3.3.2 Synchronous Sequential Circuits; 3.3.3 Synchronous and Asynchronous Circuits; 3.4 FINITE STATE MACHINES; 3.4.1 FSM Design Example; 3.4.2 State Encodings; 3.4.3 Moore and Mealy Machines; 3.4.4 Factoring State Machines; 3.4.5 FSM Review; 3.5 TIMING OF SEQUENTIAL LOGIC; 3.5.1 The Dynamic Discipline; 3.5.2 System Timing; 3.5.3 Clock Skew; 3.5.4 Metastability; 3.5.5 Synchronizers; 3.5.6 Derivation of Resolution Time; 3.6 PARALLELISM; 3.7 SUMMARY; Exercises; Untitled; Chapter 4 Hardware Description Languages; 4.1 INTRODUCTION

4.1.1 Modules

Notes:

Description based upon print version of record.

Includes bibliographical references (p. 555-556) and index.

ISBN:

9786611227265

9781281227263

1281227269

9780080547060

0080547060

OCLC:

476217362