CMOS technology / Min-jun Kwon, editor.

Format:

Book

Contributor:

Kwon, Min-jun.

Series:

Electrical engineering developments series.

Electrical engineering developments

Language:

English

Subjects (All):

Metal oxide semiconductors, Complementary.

Physical Description:

1 online resource (262 p.)

Edition:

1st ed.

Place of Publication:

New York : Nova Science Publishers, c2011.

Language Note:

English

Summary:

Complementary metal-oxide-semiconductor (CMOS) is a technology for constructing integrated circuits. This book presents research data in the study of CMOS technology, including CMOS lithography; the variability and reliability in ultra-scaled CMOS devices; linear and non-linear applications of CMOS DVCC; and, more.

Contents:

Intro

CMOS TECHNOLOGY

LIBRARY OF CONGRESS CATALOGING-IN-PUBLICATION DATA

CONTENTS

PREFACE

Chapter 1 PRINCIPLES, INTEGRATION AND CHALLENGES OF LITHOGRAPHY TECHNOLOGY FOR DEEP NANO-SCALE CMOS PATTERNING

ABSTRACT

1. INTRODUCTION

2. EUV TOOL DEVELOPMENT: STATUS AND REQUIREMENTS

3. EUV LITHOGRAPHY CHALLENGES

3.1. EUV Source Power Requirement

3.2. EUV Mask Defect

3.3. EUV Mask Inspection

4. EUV SOURCE DEVELOPMENT

4.1. Gas Discharge Produced Plasma

4.2. Laser Produced Plasma

5. EUV RESIST DEVELOPMENT

6. EUV IMAGING WITH MULTILAYER MIRRORS

6.1. EUV Mirror Structure

6.2. Flare Impact on EUV Imaging

7. EUV PHASE-SHIFTING MASKS

8. SUMMARY OF MASK BASED EUV LITHOGRAPHY

9. MASKLESS EUV LITHOGRAPHY

10. IMAGING THEORY OF PROJECTION LITHOGRAPHY

10.1. Basic Principles of Electromagnetic Field and Geometrical Optics

10.2. Light Propagation and Spatial Coherence

10.3. Spectral Analysis of Image Formation

10.4. Oblique Illumination and Partial Coherence

10.5. Resolution Enhancement Techniques

10.6. DUV Immersion Lithography

10.7. Vector Imaging Theory and Polarization

10.8. EUV Multilayer Reflective Optics

11. MULTIPLE PATTERNING TECHNOLOGIES

11.1. Double Patterning

11.2. Self-aligned Triple and Quadruple Patterning

SUMMARY

REFERENCES

Chapter 2 VARIABILITY AND RELIABILITY IN ULTRA-SCALED MOS DEVICES: EVALUATION AT THE NANOSCALE AND IMPACT ON DEVICE AND CIRCUIT FUNCTIONALITY

INTRODUCTION

NANOSCALE CHARACTERIZATION OF GATE OXIDE RELATED VARIABILITY

Experimental Set-up and Sample Description

Physical Characterization

Electrical Characterization of the as-Grown High-K Stacks

Charge Trapping after Electrical Stress

TIME-DEPENDENT VARIABILITY OF DEVICES AND CIRCUITS.

Variability and Aging Experimental Characterization

SPICE Modelling of the Aging Mechanisms and Montecarlo Simulation of Device Variability

SPICE Simulations: from Device Time-Dependent Variability to Circuit Reliability

CONCLUSIONS

ACKNOWLEDGMENTS

Chapter 3 LINEAR AND NON-LINEAR APPLICATIONS OF CMOS DVCC

I. INTRODUCTION

II. SURVEY OF SOME EXISTING DVCC BASED CIRCUITS

A. Amplifiers

B. Integrators

C. Filters with Bi-Linear Transfer Functions

D. Biquadratic Filters

E. Sinusoidal Oscillators and Function Generators

III. PROPOSED CIRCUITS

A. Linear Equation Solver

B. Linear Programming Circuit

C. Quadratic Programming Circuit

D. Implementation of Logic Gates Using DVCC

IV. SIMULATION RESULTS

CONCLUSION

Chapter 4 COMPACT MODELING OF MULTI-GATE MOSFET INCLUDING HOT-CARRIER EFFECTS

2. DEFECTS IN CMOS-BASED DEVICES

2.1. Bulk Defects

2.1.1. Origin of the problem

2.1.2. Characterization methods

2.2. Hot Carrier

2.2.1. Origin of the problem

2.2.2. Device Parameters degradation

3. MODELING OF MULTI-GATE MOSFETS INCLUDING HOT-CARRIERS EFFECTS

3.1. Hot-Carriers Effects in Subthreshold Regime

3.1.1. Surface potential

3.1.2. Threshold voltage

3.1.3. Subthreshold current

3.1.4. Subthreshold swing

3.2. Hot-Carriers Effects in Saturation Regime

3.2.1. Drain current model

3.2.2. Small-signal model parameters

4. CONCLUDING REMARKS

Chapter 5 MOSFET MODELING: RELIABILITY AND VALIDATION FOR ANALOG/RF IC DESIGN

2. ANALOG/RF MOSFET MODELS OVERVIEW, ACCURACY REQUIREMENTS AND VALIDATION

A. RF MOS Transistor Models and Benchmark Testing

i. RF modelling accuracy requirements

ii. MOSFET model benchmark testing for analog/RF IC design.

B. PSP: Brief Overview of the New CMC Standard Compact MOS Model [8]

C. HiSiM and EKV MOSFET models brief overview

3. ANALOG/RF MOSFET MODELLING GENERAL APPROACH ANDS CRITICAL PARAMETERS [5]

4. MOSFET MODELLING IN RELATION TO ANALOG / RF CIRCUITS CRITICAL PERFORMANCE PARAMETERS ESTIMATION

5. SUMMARY

Chapter 6 CATALOG OF VERSATILE QUADRATURE OSCILLATORS USING GROUNDED COMPONENTS

2. AVAILABLE OSCILLATORS

3. PROPOSED CIRCUITS

3.1. Circuits' Description

3.2. Circuit Analysis

4. NON IDEALITIES AND PARASITIC STUDY

4.1. Non Ideal Analysis

4.2. Effect of DVCC Parasitics

5. SIMULATION RESULTS

5. AN EXTENDED APPLICATION

Chapter7FEEDTHROUGH:ANENERGYEFFICIENTCMOSLOGICFAMILYFORARITHMETICCIRCUITS

Abstract

1.Introduction

2.FTLPrincipleofOperation

3.CMOS-FTLevaluation

3.1.Proposedstructures

3.2.AnalysisResultsfortheBasicCells

3.3.Applications

4.DesignExamples

5.SensitivityAnalysis

6.RCAImplementation

7.Monte-CarloAnalysis

8.RCATestChip

9.DiscussionandFurtherWork

10.Conclusion

References

Chapter 8 DISCUSSION ON 1/F NOISE IN CMOS TRANSISTORS: MODELLING-SIMULATION AND MEASUREMENT TECHNIQUES*

1.1. INTRODUCTION

1.2. FLICKER NOISE MODELLING AND SIMULATION

1.2.1. The Empirical and the Typical 1/f Noise Models

A. Simple empirical model

B. Number fluctuation model and mobility fluctuation model

1.2.2. Combined Models

1.2.3. Noise Simulation Using the BSIM MOSFET Model in Software Packages

Flicker Noise Simulation Models

Critical Issues on the Unified 1/f Noise Models

1.2.4. Impact of Scaling down Technologies on 1/f Noise

1.3. NOISE REDUCTION

1.3.1. 1/f Noise under Switched Bias Conditions

Applications of the Switched Bias Technique.

1.3.2. Available Methods

B. DC Offset and Drift Reduction Techniques

C. Reduce the Upconversion of 1/f Noise

D. Phase-Locked Loop (PLL)

E. The switched biasing approach

Cycling between Strong Inversion and Accumulation

1.4. MEASUREMENT OF LOW FREQUENCY NOISE IN MOSFETS

1.4.1. Low Frequency Noise Measurement Technique under Constant Bias

1.4.2. Low-Frequency Noise Measurement Technique under Switched Bias

INDEX.

Notes:

Description based upon print version of record.

Includes bibliographical references and index.

Description based on print version record.

ISBN:

1-61761-545-5

OCLC:

833300441