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Wafer-level testing and test during burn-in for integrated circuits / Sudarshan Bahukudumbi, Krishnendu Chakrabarty.

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Format:
Book
Author/Creator:
Bahukudumbi, Sudarshan.
Contributor:
Chakrabarty, Krishnendu.
Series:
Artech House integrated microsystems series.
Artech House integrated microsystems series
Language:
English
Subjects (All):
Integrated circuits--Testing.
Integrated circuits.
Integrated circuits--Wafer-scale integration.
Semiconductors--Testing.
Semiconductors.
Physical Description:
1 online resource (214 p.)
Edition:
1st ed.
Place of Publication:
Boston : Artech House, 2010.
Language Note:
English
Summary:
Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing. Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constraints. Moreover, this book helps practitioners address the issue of enabling next generation products with previous generation testers. Practitioners also find expert insights on current industry trends in WLTBI test solutions.
Contents:
Wafer-Level Test and Burn-In: Industry Practices and Trends
Resource-Constrained Testing of Core-Based ScCs
Defect Screening for "Big-D/Small-A" Mixed-Signal SoCs
Wafer-Level Test During Burn-In: Test Scheduling for Core-Based SoCs
Wafer-Level Test During Burn-In: Power Management by Test-Pattern Ordering
Wafer-Level Test During Burn-In: Power Management by Test-Pattern Manipulation.
Notes:
Description based upon print version of record.
Print version record.
Includes bibliographical references and index.
ISBN:
1-59693-990-7
OCLC:
796382946

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