Logic-timing simulation and the degradation delay model / Manuel J. Bellido, Jorge Juan, Manuel Valencia.

Format:

Book

Author/Creator:

Bellido, Manuel J., 1964-

Contributor:

Juan Chico, Jorge.

Valencia, Manuel.

Language:

English

Subjects (All):

Computer simulation.

Mathematical models.

Physical Description:

1 online resource (286 p.)

Edition:

1st ed.

Place of Publication:

London : Imperial College Press, c2006.

Language Note:

English

Summary:

This book provides the reader with an extensive background in the field of logic-timing simulation and delay modeling. It includes detailed information on the challenges of logic-timing simulation, applications, advantages and drawbacks. The capabilities of logic-timing are explored using the latest research results that are brought together from previously disseminated materials. An important part of the book is devoted to the description of the "Degradation Delay Model", developed by the authors, showing how the inclusion of dynamic effects in the modeling of delays greatly improves the appl

Contents:

Prologue; Preface; Contents; 1 Fundamentals of Timing Simulation; 2 Delay Models: Evolution and Trends; 3 Degradation and Inertial Effects; 4 CMOS Inverter Degradation Delay Model; 5 Gate-Level DDM; 6 Logic Level Simulator Design and Implementation; 7 DDM Simulation Results; 8 Accurate Measurement of the Switching Activity; References; Index

Notes:

Description based upon print version of record.

Includes bibliographical references and index.

ISBN:

9786611867096

9781281867094

1281867098

9781860947360

1860947360

OCLC:

476063790