Design for at-speed test, diagnosis, and measurement / edited by Benoit Nadeau-Dostie.

Format:

Book

Contributor:

Nadeau-Dostie, Benoit.

Series:

Frontiers in electronic testing.

Frontiers in electronic testing

Language:

English

Subjects (All):

Integrated circuits--Testing.

Integrated circuits.

Electronic apparatus and appliances--Testing.

Electronic apparatus and appliances.

Physical Description:

1 online resource (258 p.)

Edition:

1st ed. 2000.

Place of Publication:

Boston : Kluwer Academic, c2000.

Language Note:

English

Summary:

Design for AT-Speed Test, Diagnosis and Measurement is the first book to offer practical and proven design-for-testability (DFT) solutions to chip and system design engineers, test engineers and product managers at the silicon level as well as at the board and systems levels. Designers will see how the implementation of embedded test enables simplification of silicon debug and system bring-up. Test engineers will determine how embedded test provides a superior level of at-speed test, diagnosis and measurement without exceeding the capabilities of their equipment. Product managers will learn how the time, resources and costs associated with test development, manufacture cost and lifecycle maintenance of their products can be significantly reduced by designing embedded test in the product. A complete design flow and analysis of the impact of embedded test on a design makes this book a `must read' before any DFT is attempted.

Contents:

Technology Overview

Memory Test and Diagnosis

Logic Test and Diagnosis

Embedded Test Design Flow

Hierarchical Core Test

Test and Measurement for PLLs and ADCs

System Test and Diagnosis

System Reuse of Embedded Test.

Notes:

Description based upon print version of record.

Includes bibliographical references.

ISBN:

1-280-20031-6

9786610200313

0-306-47544-8

OCLC:

923696405