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2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) : 2013 September 29, 2013 - Oct. 4, 2013, Montreal, Canada / IEEE/ACM/IFIP International Conference on Hardware/Software Codesign & System Synthesis.
- Format:
- Book
- Conference/Event
- Conference Name:
- IEEE/ACM/IFIP International Conference on Hardware/Software Codesign & System Synthesis, author.
- Language:
- English
- Subjects (All):
- System design--Congresses.
- System design.
- Systems software--Congresses.
- Systems software.
- Embedded computer systems--Congresses.
- Embedded computer systems.
- Physical Description:
- 1 online resource (321 pages) : illustrations
- Other Title:
- 2013 International Conference on Hardware/Software Codesign and System Synthesis
- Hardware/Software Codesign and System Synthesis
- Place of Publication:
- Piscataway, NJ : IEEE, 2013.
- Contents:
- AADLv2, An Architecture Description Language For The Analysis And Generation Of Embedded Systems
- Cross-Layer Reliability Modeling And Optimization For Embedded Systems Under Process Variations
- Mixed-Criticality Systems: Design And Certification Challenges
- Reducing Inter-Core Cache Contention With An Adaptive Bank Mapping Policy In DRAM Cache
- A Reconfigurable Real-Time SDRAM Controller For Mixed Time-Criticality Systems
- A DRAM-Flash Index For Native Flash File Systems
- WHISK: An Uncore Architecture For Dynamic Information Flow Tracking In Heterogeneous Embedded SoCs
- Synthesis-Friendly Techniques For Tightly-Coupled Integration Of Hardware Accelerators Into Shared-Memory Multi-Core Clusters
- Embedded Supercomputing In FPGAs With The VectorBlox MXP Matrix Processor
- DHeating: Dispersed Heating Repair For Self-Healing NAND Flash Memory
- Learning The Optimal Operating Point For Many-Core Systems With Extended Range
- Voltage/Frequency Scaling
- Online OLED Dynamic Voltage Scaling For Video Streaming Applications On Mobile Devices
- pvFPGA: Accessing An FPGA-Based Hardware Accelerator In A Paravirtualized Environment
- CMSM: An Efficient and Effective Code Management For Software Managed Multicores
- On The Automatic Generation Of GPU-Oriented Software Applications From RTL IPs
- Run-Time Adaption For Highly-Complex Multi-Core Systems
- Bound-Oriented Parallel Pruning Approaches For Efficient Resource Constrained Scheduling Of High-Level Synthesis
- Improving Polyhedral Code Generation For High-Level Synthesis
- System Level Synthesis OfHardware For DSP Applications Using Pre-Characterized Function Implementations
- A Cyber-Physical System Approach To Artificial Pancreas Design
- Instruction Set Extensions For Dynamic Time Warping
- Scalable NoC-Based Architecture Of Neural Coding For New Efficient Associative Memories
- Design Space Exploration And Parameter Tuning For Neuromorphic Applications
- Hardware Neural Network Accelerators
- Embedded Neuromorphic Vision Systems
- Bio-Inspired Ultra Lower-Power Neuromorphic Computing Engine For Embedded Systems
- IVaM: Implicit Variant Modeling And Management For Automotive Embedded Systems
- Improved Formal Worst-Case Timing Analysis Of Weighted Round Robin Scheduling For Ethernet
- Dimensioning And Configuration Of EES Systems For Electric Vehicles With Boundary-Conditioned Adaptive Scalarization
- VarEMU: An Emulation Testbed For Variability-Aware Software
- Automatic Generation Of Compact Formal Properties For Effective Error Detection
- Automatic Refinement Of Requirements For Verification Throughout The SoC Design Flow
- ARGO: Aging-Aware GPGPU Register File Allocation
- An Energy And Deadline Aware Resource Provisioning, Scheduling And Optimization Framework For Cloud Systems
- Designing A Residential Hybrid Electrical Energy Storage System Based On The Energy Buffering Strategy
- Panappticon: Event-Based Tracing To Measure Mobile Application And Platform Performance
- Multi-Mode Monitoring For Mixed-Criticality Real-Time Systems
- A Variability-Aware OpenMP Environment For Efficient Execution OfAccuracy-Configurable Computation On Shared-FPU Processor Clusters
- Automated, Retargetable Back-Annotation For Host Compiled Performance And Power Modeling
- Author Index.
- Notes:
- Description based on publisher supplied metadata and other sources.
- Includes index.
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