2010 International Conference on Field Programmable Logic and Applications

Format:

Book

Author/Creator:

Institute of Electrical and Electronics Engineers, author.

Contributor:

ieee, Contributor.

Language:

English

Subjects (All):

Computer architecture--Congresses.

Computer architecture.

Physical Description:

1 online resource

Place of Publication:

[Place of publication not identified] IEEE 2010

Language Note:

English

Summary:

Because of the redundancy factors of FPGAs, there is a performance gap between FPGAs and ASICs. In this paper, we propose a small-memory logic cell, COGRE, to minimize the FPGA area. Our approach is to investigate the appearance ratio of the logic functions in a circuit implementation. Moreover, we group the logic functions on the basis of the NPN-equivalence class. The results of our investigation show that only small portions of the NPN-equivalence class can cover large portions of the logic functions used to implement circuits. Further, we found that NPN-equivalence classes with a high appearance ratio can be implemented by using a small number of AND gates, OR gates, and NOT gates. On the basis of this observation, we develop 5-input and 6-inputCOGRE architectures composed of several NAND gates and programmable inverters. The experimental results show that the logic area in 6-COGRE is 46.3% smaller than that in 6-LUT. The logic area of 5-COGRE is 32.6% smaller than that of 5-LUT and 10.0% smaller than that of 4-LUT. Further, the total number of configuration memory bits in 6-COGRE is32.1% smaller than the number of configuration memory bits in 6-LUT.

Notes:

Bibliographic Level Mode of Issuance: Monograph

ISBN:

9781424478439

142447843X