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2011 Symposium on VLSI Circuits
- Format:
- Book
- Author/Creator:
- Institute of Electrical and Electronics Engineers (IEEE), author, issuing body.
- Language:
- English
- Subjects (All):
- Computers--Circuits--Congresses.
- Computers.
- Integrated circuits--Very large scale integration--Congresses.
- Integrated circuits.
- Physical Description:
- 1 online resource : illustrations
- Place of Publication:
- [Place of publication not identified] IEEE 2011
- Language Note:
- English
- Summary:
- We describe a DAC which can operate at up to 7.2 GSa/s with 14-bit resolution or up to 12 GSa/s with 12-bit resolution. It uses a segmented architecture, with an R/2R ladder for the 10 LSBs; distributed resampling is applied to all current sources. The DAC achieves an SFDR of 77 dB at low output frequencies and an SFDR of 67 dB and an SNR of 62 dB from DC to 3 GHz. It demonstrates a phase noise of -157 dBc/Hz at 10 kHz from a 1 GHz carrier, 22 dB better than synthesized signal generation instruments. The DAC is built in a 165-GHz fT, 130-nm BiCMOS process and packaged in a 780-ball BGA.
- Notes:
- Bibliographic Level Mode of Issuance: Monograph
- ISBN:
- 9781467317276
- 1467317276
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